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Design Electrical Engineer

Location:
Palo Alto, California, 94301, United States
Salary:
75000
Posted:
May 28, 2010

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Vince Gaydarzhiev

*** ********* *** *, **** Alto, CA 94301

sx56ea@r.postjobfree.com

+1 407 *** ****

Education

University of Southern California, Los Angeles, CA MS, Electrical Engineering,

University of Central Florida, Orlando, FL BS, Electrical Engineering, Microelectronics , Honors

Experience

Electrical Engineer, Los Angeles, CA Beckman Coulter, Inc

| Fall 2008 – Fall 2009 Cumulative GPA: 3.5/4.0

| Fall 2002 – Fall 2007 Cumulative GPA: 3.9/4.0

| May 2009 – August 2009

Research and Development Department, Manager: Mark Gomez Internship in the Analog Design Team - Worked on a DNA analysis device’s communication board - ASIC Design

- GPIB implementation and communication - Old NAT4882 ASIC changed to TNT4882 or NAT7210 RoHS compliant, 2 prototypes completed - Software tools, register transfer, schematics and layout using OrCAD tools - New NAT7210 tested fully working on an MDQ DNA analysis device

Research Assistant, Los Angeles, CA | August 2008 – January 2010 University of Southern California, Electrical Engineering Department Nanoelectronics Lab, Advisor Dr. Chongwu Zhou

Nanotechnology, nanoelectronics, and bionanotechnology; RF nanotransistors, synthesis and applications of carbon nanotubes and nanowire, Making of graphene samples from graphite flakes, CVD, oxidation, growth, etching, deposition, evaporation, AFM confirming one or multiple-layer graphene, lithography, SEM, EFM, Basic logic blocks made of CNT.

PCB Design Engineer, Orlando, FL | August 2007 – July 2008 ApeCor - AC-DC converter design, using Cadence tools for schematic and layout of the main power board

Microelectronics, Energy Harvesting, Electric Power, Biomechanics, Schematic Capture, PCB/EMC design using high-speed digital design rules, Digital control, Debugging, Low and high power design, Converter design, USB/RS232 integration

Venceslav Gaydarzhiev

Research Assistant, Orlando, FL | January 2006 – July 2008 University of Central Florida, Electrical and Computer Engineering Department

Power Electronics Lab, Advisor Dr. Issa Batarseh

Biomechanics, Energy Harvesting, Electric Power, Schematic Capture, PCB/EMC design using high speed digital design rules, Digital control, Debugging, Low and high power design, Converter design, USB/RS232 integration

Research Assistant, Orlando, FL | Fall 2004 – Summer 2006 University of Central Florida, Electrical and Computer Engineering Department

Robotics Lab, Advisor Dr. Zhihua Qu

Advanced controls, Robotics, Autonomous Vehicles, 802.11 integration, Sensor development, integration and testing

Recent Electrical Engineering Graduate Coursework / Projects

• VLSI CAD DRAM and SRAM Design (EE577) – Adders, DRAM vs. SRAM, IC Design Projects: 128-bit Ripple Carry Adder

D-type Flip-Flop and a phase-accumulator 16-bit register with synchronous reset 1.28KBit SRAM with 10-bit wide words (using tsmc03 tech with Cadence) 16x16-bit Multiplier, Pipelining

• Modern Solid State Devices (EE537) • MOS VLSI IC Design (EE477) – Flip-Flops, Latches

- Final project - Digital neurons, neural network design with excitatory and inhibitory I/O

• Mixed-Signal Integrated Circuit Design (EE536) • Biomedical Engineering (BME533) • Solid State Processing and Integrated Circuits (EE504) – PN junctions, MOSFETs, BJTs, Photolithogr.

- Final project – complete fabrication of a working CMOS Si wafer with basic logic blocks

• Analog and Non-Linear Integrated Circuit Design (EE479) • Semiconductor Device Modeling and Simulation (EE5353) • Power Electronics II (EE6246) • Power Electronics (EE5245)

• Digital Control Systems (EE5630) • Digital Signal Processing Applications (EE5513) • Digital Signal Processing I (EE4750) • Advanced Electronics (EE4309)

Skills

DRAM and SRAM design, design flow and design verification, CMOS IC design, ASICs, simulation (SPICE, Cadence PCB Layout Design, hspice, Orcad Capture, MATLAB & Simulink, Eagle, LabView, MathCAD, Multisim, Mathematica, Ansoft Simplorer, NanoScope, T ecPLO T), static and dynamic logic implementation, adders, lab experience growing CNT samples, lithography, GPIB and USB implementation, Verilog, C++, RTL, Assembly, Timing verification, DRC, LVS, parasitic extraction, logic design and simulation, pipelining, decoders, mixed-signal design, transistor-level analysis, data paths



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