ASIC UVM Verification Engineer
Resume:
Karthik Nalaparaju
************@*****.*** / 785-***-****
Professional Summary:
ASIC Design Verification Engineer with 8 years of experience in verifying ASIC/SoC designs using SystemVerilog and UVM. Experienced in developing and maintaining testbenches, writing directed and constrained-random test cases, and checking design functionality against verification requirements. Hands-on experience with functional coverage, SVA assertions, simulation debugging, and regression testing to identify design issues and improve test quality. Familiar with protocol verification, waveform analysis, and Linux-based development environments. Comfortable working with RTL design teams to troubleshoot failures, track verification progress, and support coverage closure throughout the development cycle.
Technical Skills:
HDL Languages: Verilog, SystemVerilog
Verification Methodologies: Functional Verification, Directed Testing, Constrained-Random Verification, Coverage-Driven Verification
Verification Framework: UVM, Testbench Development, Sequences, Drivers, Monitors, Scoreboards
Assertions: SystemVerilog Assertions (SVA), Assertion-Based Verification
Functional Coverage: Covergroups, Coverpoints, Cross Coverage, Coverage Analysis, Coverage Closure
Protocol Verification: AXI4, AHB, APB, Valid-Ready Handshake, Read/Write Transactions
SoC/IP Verification: RTL Functional Verification, IP-Level Verification, Register Verification, Reset Verification, Data-Path Verification
Simulation Tools: Synopsys VCS, Siemens QuestaSim, Cadence Xcelium
Debugging Tools: Verdi, SimVision, Waveform Analysis, Simulation Log Analysis, RTL Debugging
Regression Testing: Regression Execution, Failure Analysis, Test Reproduction, Regression Reporting
Scripting Languages: Python, Bash, Shell Scripting
Operating Systems: Linux, Unix
Version Control: Git, SVN
Automation Tools: Make, Regression Automation Scripts
Verification Planning: Verification Plans, Test Scenarios, Test Specifications, Requirement Traceability
Defect Tracking and Collaboration: Defect Tracking, Coverage Reporting, Root-Cause Analysis, RTL Designer Collaboration
Professional Experience:
L3Harris Technologies LLC August 2024 - till now
Role: ASIC Design Verification Engineer
Project title: ASIC/FPGA RTL Functional Verification and UVM-Based Protocol Validation
Responsibilities:
●Developed and maintained reusable SystemVerilog/UVM testbenches to verify RTL functionality, control logic, register interfaces, and subsystem-level design behavior.
●Prepared block-level verification plans from RTL specifications, covering reset sequencing, register access, control-path operations, interrupt handling, and error conditions.
●Created directed and constrained-random test scenarios to validate normal operating conditions, boundary cases, invalid transactions, and corner-case behavior.
●Developed UVM sequences, drivers, monitors, and scoreboards to generate stimulus, capture DUT responses, and verify expected transaction behavior.
●Implemented SystemVerilog Assertions (SVA) to check protocol handshakes, reset behavior, control-signal transitions, and design-specific timing requirements.
●Developed functional coverage models to track verification scenarios, register operations, state transitions, transaction combinations, and error-handling conditions.
●Analyzed functional coverage reports and identified untested scenarios, adding targeted sequences to improve coverage closure against verification goals.
●Executed RTL simulations and regression suites using QuestaSim/VCS to validate design changes, identify functional mismatches, and confirm previously passing scenarios remained stable.
●Debugged RTL and testbench failures by analyzing simulation logs, waveform traces, signal transitions, and assertion failures to isolate root causes.
●Collaborated with RTL design engineers to reproduce functional defects, review simulation evidence, and verify corrective changes through focused and full-regression testing.
●Used Linux-based development environments and Git for testbench maintenance, source-code version control, regression management, and verification change tracking.
●Documented test results, failure analysis, coverage status, and unresolved verification issues to support design reviews and project-level verification milestones.
●Developed SystemVerilog/UVM-based verification environments to validate RTL functionality, control logic, and protocol interfaces across FPGA/SoC subsystems.
●Created directed and constrained-random test scenarios for AXI4/AHB/APB bus transactions, register accesses, burst transfers, handshake behavior, and error-response conditions.
●Developed UVM sequences, monitors, and scoreboards to verify DMA transaction handling, data integrity, request/response ordering, and interface-level functionality.
●Implemented SystemVerilog Assertions (SVA) to validate protocol handshakes, reset sequencing, signal stability, transaction completion, and design-specific timing requirements.
●Developed functional coverage models for protocol transactions, state transitions, boundary conditions, error scenarios, and corner-case verification.
●Performed RTL simulation, regression testing, and root-cause analysis using QuestaSim/VCS, analyzing waveforms, assertion failures, and simulation logs to isolate design and testbench issues.
Technical Environment: SystemVerilog, UVM, SVA, Functional Coverage, Verification Planning, AXI4/AHB/APB, DMA, PCIe, Ethernet, RTL Debug, Regression Testing, Protocol Verification, QuestaSim/VCS, Linux, Git.
MosChip Technologies, Madison, WI June 2022 - Jul 2024
Role: ASIC Verification Engineer
Project: SoC Bus Interface and Data Transfer Verification
●Developed reusable UVM agents, drivers, monitors, and sequences for verifying bus-interface functionality at IP and subsystem levels.
●Created transaction-level test scenarios to verify AXI/APB/AHB read-write operations, response handling, back-to-back transfers, and protocol corner cases.
●Implemented scoreboard checks to validate transaction ordering, address handling, and read/write data consistency.
●Used constrained-random stimulus to exercise wait states, response errors, and concurrent interface activity.
●Developed functional coverage models for transaction types, burst lengths, response conditions, and protocol-state combinations.
●Debugged protocol violations and data mismatches using simulation logs, waveform viewers, and assertion failures.
●Ran nightly regressions, reviewed failure summaries, and coordinated with RTL engineers to verify fixes.
●Developed reusable UVM agents, drivers, monitors, and sequences to verify bus-interface functionality at IP and subsystem levels.
●Created transaction-level test scenarios to validate AXI4/APB/AHB read-write operations, response handling, back-to-back transfers, and protocol corner cases.
●Implemented UVM scoreboards and transaction checkers to validate transaction ordering, address handling, and read/write data consistency.
●Applied constrained-random stimulus to exercise wait states, response errors, burst transfers, and concurrent interface activity.
●Developed functional coverage models to track transaction types, burst lengths, response conditions, and protocol-state combinations.
Tools: SystemVerilog, UVM, SVA, AXI4, AHB, APB, Functional Coverage, Constrained-Random Verification, QuestaSim, VCS, Linux, Git, RTL Debug, Regression Testing.
Mirafra Techologies May 2020 – May 2022
Role: Design Verification Engineer
Project: IP-Level Control Logic and Register Verification
Responsibilities:
●Prepared block-level verification plans from RTL specifications, including register access, reset values, interrupts, and control-path behavior.
●Developed SystemVerilog test scenarios for register programming, read/write permissions, reset recovery, and invalid access conditions.
●Used UVM sequences and register-model-based testing where supported by the project environment to validate register behavior.
●Applied assertions to check reset sequencing, handshake protocols, and expected control-signal transitions.
●Debugged simulation failures in Cadence Xcelium or QuestaSim by tracing signal dependencies and reviewing transaction logs.
●Used Python and shell scripts to summarize regression results, identify recurring failures, and simplify repetitive test execution.
●Reviewed code and functional coverage reports to identify missing conditions and add targeted verification scenarios.
Technical Skills: SystemVerilog, UVM, SVA, Xcelium/QuestaSim, Python, Shell scripting, Linux, Git.
Tata Elxsi - HYD, IND June 2017 - Oct 2019
Role: Associate Design Verification Engineer
Responsibilities:
●Wrote basic SystemVerilog test cases to verify RTL functionality, reset behavior, and control-signal transitions.
●Developed directed test scenarios to check read/write operations and basic data-transfer functionality.
●Supported UVM testbench development by updating sequences, running tests, and checking simulation results.
●Verified basic AXI/APB transactions and handshake behavior against design specifications.
●Used QuestaSim/VCS waveform viewers to investigate signal mismatches and simulation failures.
●Added simple SVA assertions to check reset conditions and valid-ready handshake behavior.
●Ran regression tests, reviewed simulation logs, and reported failures to senior verification engineers.
●Updated functional coverage points and added test cases for scenarios identified as missing.
●Used Linux commands and basic shell scripts to execute simulations and organize test results.
Technical Skills: Verilog, SystemVerilog, Basic UVM, SVA, AXI/APB, QuestaSim, Linux, Git, Simulation Debugging, Functional Coverage.
Education:
Bachelors in Electronics and Communications Engineering, JNTUH 2016
Masters in Management and Information Systems, Pittsburg State University 2021
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