Design Verification Engineer (UVM/SystemVerilog)

Kartheek Morisetti

*****************@*****.*** 945-***-**** Fremont, California

LINKS

LinkedIn: kartheekmorisetti

SKILLS

PROGRAMMING

• System Verilog

• UVM

• PAV-UPF

• PA-GLS

• C/C++

• Verilog

• Python/Perl/Shell

DV SKILLS

• Constraint Randomization

• Assertions

• Test Plan Development

• TB Components Development

• Test Cases Development

• Regression

• Coverage - Code/Func

• AMBA - APB Protocol

• AMBA - AHB Protocol

• AMBA - AXI-Lite Protocol

• SPI

TOOLS

• VCS

• Verdi

• Cadence Xcelium

• Questa-sim

• AI: Claude/Copilot/Metamate

EDUCATION

JNTU,SULTANPUR

B.Tech

Electronics & Communication

Engineering

May, 2017

SUMMARY

Enthusiastic Electronics Engineer specializing in Design Verification, with hands-on experience in SystemVerilog and UVMmethodology.

EXPERIENCE

DESIGNVERIFICATIONENGINEER Marvell Technology, Santaclara January 2026 - Now

• Developed and verified testbenches for B-PHY networking subsystem using UVM, SystemVerilog, and industry-standard EDA tools.

• Developed UVM test cases supporting SS-level stimulus generation and driving bus-level signal activity to Accelerators, DDR, SMEM, X-bar blocks.

• Integrated and validated IP/Subsystem-level changes from customer environments into local branches.

• Deployed performance optimizations to improve CT by 50% and RT efficiency by 20%.

DESIGN VERIFICATION ENGINEER META, Sunnyvale

Jun 2025 - Dec 2025

• Developed and verified testbenches for ML Accelerator Subsystem using UVM, SystemVerilog, C.

• Verified Clocking, Power unit blocks ensuring reliable SoC/SS-level compliance using an ARM Cortex-M7 MCU.

• Worked on reusing and enhancing the UVM verification components

(sequence items, components), integrating corner-case stimulus.

• Developed and verified functional coverage.

LEADDESIGNVERIFICATIONENGINEER Qualcomm Technology, india Oct 2022 - Mar 2025

• Developed and verified PA testbenches for Camera Subsystem using UPF, UVM, SystemVerilog.

• Owned and executed Power Aware verification with low power design techniques - clock and power gating, frequency scaling, memory/logic retention.

• Developed PA Test plan, Test-bench bring up and enhancing the UVM verification components, Assertion checks.

• Improved low-power assertion coverage, PST coverage, and CDC assertion checks.

• Contributed to PA-GLS testbench bring-up, debug, and verification of PA gate-level simulation flows.

• Collaborated with cross-functional teams (Design, SoC, Synth teams) to ensure the highest design quality.

PRODUCT ENGINEER Synopsys, india

Feb 2018 - Sep 2021

• Developed and verified RAL testbenches for DDR IP using UVM, SystemVerilog, C, and industry-standard EDA tools.

• Developed RAL test bench components Register Block and Registers class configuration, test cases.

• Owned and executed verification of the PUF IP within the FPGA CPU based SDM subsystem.

• Component Owner for Compile, Partition-Compile modules in VCS — accountable for end-to-end feature validation, and quality sign-off across every release cycle.

• Responsible for developing Test plan, UVM, SystemVerilog, Verilog, C test cases and Improving the Code coverage.

• Performed root-cause analysis (RCA) for complex customer-reported issues in collaboration with R&D teams.

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