Digital ASIC/FPGA Verification Engineer (UVM)

PRASHRAY NAGAR

Berkeley, California 919-***-**** *************@*****.*** LinkedIn GitHub

Digital ASIC / FPGA Design Verification Engineer with hands-on experience in SystemVerilog/Verilog RTL microarchitecture, UVM-based functional verification, Cocotb, Python, and FPGA emulation using Xilinx Vivado. Architected reusable peripheral IP blocks across UART, SPI, I2C, and USB, built constrained-random verification environments with SVA and coverage metrics, and resolved CDC and timing-closure bottlenecks. Published IEEE researcher focused on energy-efficient VLSI architectures. EDUCATION

Master of Computer Engineering (GPA:3.3/4.0)

North Carolina State University

Aug 2024 - May 2026

Raleigh, NC

Courses: ASIC and Verification Design, Microprocessor Architecture, Parallel Computing Bachelor of Electronics and Communication (GPA:3.5/4.0) Charusat University

Jul 2020 - May 2024

Anand, India

Courses: VLSI Systems and Design, Embedded Systems, Networking, Data Structures, Compiler Design SKILLS

HDLs & Verification SystemVerilog, Verilog, VHDL, UVM, Cocotb, SystemVerilog Assertions, Constrained-Random Testing, Functional Coverage, RTL Functional Verification

Protocols & Buses AXI4, AXI-Lite, AHB, APB, Wishbone, Avalon-MM, I2C, SPI, UART, USB, PCIe (Fundamentals) Programming & Automation C, C++, Python, Linux Shell / Bash Scripting, TCL, Make, Git, Docker EDA Tools & Hardware Synopsys Design Compiler, PrimeTime (STA), SpyGlass (Lint/CDC), Cadence Genus, ModelSim/QuestaSim, Verilator, AMD/Xilinx Vivado (ILA, IP Integrator), Intel Quartus Prime, Xilinx Zynq / UltraScale+ WORK EXPERIENCE

FPGA Engineering Intern

Chipchop

Jul 2026 - Present

California, USA

Engineered a flexible verification and bring-up environment for an FPGA-based SoC prototype, leveraging Verilator to ensure seamless IP portability across FPGA and ASIC flows and accelerate silicon bring-up. Conducted rigorous RTL functional verification for core peripheral IPs (UART, SPI, GPIO, USB) by developing Python-based testbenches with Cocotb, collaborating directly with designers to rapidly debug and validate on-target functionality. Managed detailed test suites and defined debug heuristics for an internal AI-driven EDA tool, successfully root-causing RTL bugs with >70% fault- detection accuracy against production-representative SoC code. System Engineering Intern

Centre for Environment Education (CEE)

Jul 2023 - Oct 2023

Ahmedabad, India

Developed embedded hardware interfaces and firmware communication routines for distributed microcontrollers using SPI, I2C, and UART serial protocols.

Configured real-time operating system (RTOS) tasks and low-latency interrupt handling for multi-sensor data acquisition, synchronizing peripheral actuators with sub-100ms response times.

Engineered autonomous, power-efficient controller nodes with embedded edge-processing algorithms that reduced system false-alarm rates while operating within strict thermal and power limits.

PROJECTS

I2C Multi-Bus Verification Using Layered UVM Testbench Designed a configurable I2C Multi-Bus (IICMB) Master controller in VHDL, targeting SoC integration via Avalon-MM and Wishbone bus interfaces. Built a layered UVM testbench in SystemVerilog — agents, sequencers, and a scoreboard — to verify multi-master, multi-bus IICMB behavior. Automated regression testing across modular UVM components (agents, drivers, monitors), reaching 92% functional coverage validated through assertion-linked coverage analysis.

Simulating MESI and MOESI Cache Coherence Protocols Developed a cycle-accurate shared-memory hardware simulator to analyze and resolve bus contention bottlenecks across symmetric multiprocessing

(SMP) systems.

Modeled snooping-based MESI and MOESI finite state machines in C++, instrumenting invalidation queues, cache-to-cache data transfers, and memory-bus arbitration under parallel execution traces. Demonstrated a 13% reduction in memory-bus traffic and lower transaction latency under MOESI by leveraging Owned-state cache-to-cache data sharing.

C++ Branch Predictor Simulator for Execution Trace Analysis Designed an architectural branch predictor simulator to evaluate speculative execution performance and reduce pipeline flush penalties in high- performance superscalar cores.

Implemented and benchmarked Bimodal, Gshare, and Tournament/Hybrid prediction algorithms in C++, optimizing Pattern History Table (PHT) indexing and Branch Target Buffer (BTB) parameter sizing against SPEC benchmarks[cite: 1, 2]. Reached 90% prediction accuracy, delivering a measurable 1-point improvement over the bimodal baseline and reducing simulated pipeline stalls PUBLICATION

Emerging VLSI Technologies for High-performance AI and ML Applications View Link 2024 International Conference on Advancements in Smart, Secure and Intelligent Computing (ASSIC) 2024

Presented at 2024 International Conference on Advancements in Smart, Secure and Intelligent Computing (ASSIC) 2024, the paper explores VLSI hardware accelerators and low-power designs to optimize AI/ML performance and energy efficiency.

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