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Entry level engineer

Location:
San Jose, CA
Posted:
March 13, 2020

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Resume:

mahantvishwanath.pattanshetti@sj

Mahant Pattanshetti

SanJ os (CA),951 13 su.edu https://www.linkedin.com/in/mahant- pattanshetti / SUMMARY

-Two years of industrial experience in the Semiconductor / Power electronics industry. Electrical

Engineering graduate student with a focus on VLSI Digital Design and Verication. Multiple ASIC Design

and Verication projects in past 1.5 years based on Verilog, System Verilog and UVM. Actively looking for

job opportunities in VLSI ASIC/RTL Design and Logic Verication. EDUCATION

:

San Jose State University, San Jose, CA USA CGPA 3.18 2018-2020 MSEE, Electrical and Electronics Engineering

Visvesvarayya Technological University, Belagavi, India. CGPA 3.25 2010-2014 Bachelor of Engineering Electrical and Electronics Engineering Coursework 8: Concepts: RTL Design 8: Verication, UVM, STA, BIST, SCAN, Scripting, Synthesis, Constrained Random

Verication, Layout/Circuit Design, ASIC CMOS Design, HiSpeed CMOS circuits, Digital Design and

Advanced Computer

Architecture(CPU).

PROFESSIONAL EXPERIENCE

KPCL, Sharavathi Generating Station. Trainee Engineer Jog Falls, Karnataka, 2015-2016 0 Worked on Operation &Maintenance of altemators, excitation governing systems. 0 Worked on microprocessor and HMI interface operation of governing systems to control the varying

speed of generators.

ETA Technology Private Limited. Graduate Engineer Peenya, Bangalore, 2016 - 2017 0 Worked in Research 8: Development division and assisted in electrical design of Welding machines.

0 Worked on the NI- CRIO RTOS 9068 development System with NI LABVIEW as the application software.

0 Developed blocks in EPGA design for the application specic tests by graphical level programming.

Technical Prociency /

SKILLS

0

SKILLS

: RTL Design, Digital logic design 8: Synthesis, Pipelining, Timing Closure, Layout Design. 0 Programming 8: Scripting- UVM, Verilog, System Verilog, C, C++. 0 Tools - Synopsys Design compiler, Cadence Virtuoso, NI Lab VIEW 0 Computer Architecture MIPS Architecture, Cache organization. Academic Projects

Community-Based Verication of Multiple MIPS DUTs gSystem Verilog/UVM) gOngoing) Oct 2019-Nov 19

UVM based verication of instructional level testing on multiple MIPS processors. Pseudo random testing on multiple DUTS Sc voting on the outcome to reduce test development time.

Developing a verication structure containing multiple UVM environments, agents and scoreboards.

Using directed test cases and constrained randomization to achieve code and functional coverage.

0 Learning the importance of verication Plan and UVM based testing for industry level application.

Functional verication of 12C controller using APB bus protocol : (System Verilog /UVM) Oct 2019-Nov 19

o UVM based verication of 12C controller model placed on an APB bus associated with IMX processor.

0 Several DUTS were monitored and veried using UVM based verication environment. 0 Using the APB bus protocols we load the 12C controller by creating the sequence, sequencer and

drivers.

0 The reference model is created and compared to verify with the output signals from the DUT. 9-bit sguare root carry select adder gCadenceQ: Oct 2019-Nov 19 0 Designing a 9-bit square root carry select adder circuit using optimized gates using Cadence virtuoso

tool.

Verifying the schematic and layout of the adder, cross-checked the waveforms and generated netlists.

Debugged the design with clear DRC and LVS runs and optimized for Power, Performance, and Area.

Performing QRC analysis to extract time delay of the block and optimized it for minimal delay. Learning the importance of logic optimization, transistor sizing and overall circuit designing for a better

PPA.

Spread Spectrum correlator gVerilog) Apr 2019-May 19 0 Designed a Spread Spectrum correlator function block using Verilog. o Implemented it in 3 modules Direct Digital Synthesis, the gold code generator correlator output

calculator.

o Veried the design using a test bench and synthesized it at gate level for 333 MHz 0 Learned the importance of pipelining and gate optimization to get minimum positive slack in synthesis.

MIPS Instruction Set Architecture gVerilogQ: Apr2019-May 19 0 Designed the MIPS ISA using 5 stages and pipelining to perform dot product of the given data. 0 Created modules for the 5 staged operation of fetch, decode, execute, memory and write back. 0 Debugged and simulated the design on the RTL level. 0 Gained the importance of data, structure and control hazards and how to avoid those for better

performance.



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