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System verilog, UVM, System verilog assertions, coverage analysis

Location:
Lubbock, Texas, United States
Posted:
November 07, 2018

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Resume:

NAGA KUMAR GAJU

**** ******** *********, #****, ******, Tx-75252.

Email: ac7msq@r.postjobfree.com Phone no: +1-806-***-****

Education:

January 2017 – August2018

Texas Tech University, Lubbock, TX

Master of science in Electrical and Computer Engineering

GPA: 3.5

Auburn University, Auburn, AL

August 2016 – December 2016

Master of Science in Electrical and Computer Engineering

GPA:3.0

Sreenidhi Institute of Science and Technology, TG, INDIA

July 2012 - May 2016

Bachelor of Technology in Electronics and Communication Engineering

GPA: 3.8

Experience:

Teaching Assistant Modern Digital Systems, Texas Tech University March 2017- May 2018

Tutor individual students to complete weekly projects

Hold discussion groups consisting of a small number of students for the successful completion of course work

Intern Embedded Design, Electronics Corporation of India Limited-TG, INDIA

June 2015 – August 2015

Worked on Embedded based Security system using RFID to wirelessly identify and grant access for authorized person

Steered a team of four to successfully complete the project by managing work, organizing meetings and sharing information

Programmed microcontroller AT89C52 using Keil µVision, embedded C and Eagle CAD for PCB design and Fabrication

General Secretary, Bachpan Bachao, a non-profit organization helping children in need by collecting funds. Feb 2014 – Feb 2016

Certification:

SOC Verification using SystemVerilog – Udemy

PCB design and fabrication – Indo Global Services

Publication:

“A New Algorithm for Reversible Logic Circuit Synthesis”, Paper Id: IJERTV7IS020081, Feb 2018, International Journal of Engineering Research & Technology (IJERT), (ISSN: 2278-0181)

Developed an algorithm to realize and synthesize reversible logic based on Truth-table approach with significant reduction in number of transistors used.

Built a user-friendly windows application using python where user can input the Boolean function minimal terms and the application generates and displays the main function and the garbage function

Skills:

Knowledge of developing test plan, test bench, SystemVerilog assertions, functional & code coverage analysis, debugging, reporting and analyzing test results and developing UVM test benches for ASIC and SoC from scratch

Programming Languages: C, C++, Verilog, System Verilog, Python, Perl, Data Structures, Java, VHDL, OpenMP, X86 Assembly Language and familiarity with RTL design

Tools and IDEs: LabVIEW, Xilinx Vivado Design Suite, Keil µVision, JMP, Cadence Virtuoso, AWR, MATLAB, Visual Studio, IAR embedded workbench, CodeComposer Studio, QuestaSim, ModelSim, Synopsys VCS, Proficient in Microsoft Office

Hardware: Power Supplies, Oscilloscopes, Multimeter, Signal generator, NI my-DAQ, Keithley SMU, Logic Analyzer, Pico Ammeter, milling machine

Familiarity with standard protocols such as ARM AMBA – APB, AHB, AXI, SAS, SATA

Project Experience:

UVM based MIPS Processor Verification using SystemVerilog

Verification of 16-bit, 5 stage pipelined MIPS processor using UVM, compiled and simulated using Synopsys VCS.

100% functional coverage was achieved using Constrained Random Verification, Assertion Based Verification.

UVM Verification Environment using SystemVerilog for AMBA APB Interface

Built APB interface in UVM with monitor, checker, sequencer, driver and slave to implement the layered testbench.

Observed the APB transactions from driver to interface and the monitor reporting the interface toggling as transactions.

2x2 Ethernet Switch Verification environment using SystemVerilog

Implementation of 2x2 Ethernet switch using SystemVerilog in ModelSim

Verification environment built with constraint random packet generation, packet driver, packet monitor and packet checking

ABV based Verification of Synchronous FIFO August 2016-Sept 2016

Developed System Verilog Assertion based verification environment of FIFO buffer operations Push, Pop, Full, Empty, Read and Write. FIFO is synchronous with a single clock governing both read and write operations

Verification of NAND Flash Controller Oct 2016-Dec 2016

Designed the verification environment for verification of the NAND flash memory controller

Developed a reusable verification environment for performance verification of a NAND Flash Controller Using UVM. The verification environment includes constrained random variable generation, monitors, checkers, assertions and scoreboards to achieve verification goals

Functional Verification of DDR3 Memory Controller using UVM July 2017- Oct 2017

Generated Test Cases and Test bench for verifying DDR3 memory controller using CAN controller as master and DDR3 memory controller as a slave and AMBA AHB as the BFM

Developed Cross Domain Clocking block using Asynchronous FIFO. Verified the Read/Write operations of the memory controller

Design of 16-bit RISC ISA processor with pipelining feature and ALU Verification November 2016

Designed a 16-bit RISC processor using Verilog that can implement a set of instructions and can support pipelining and implementation on FPGA. Resolved data dependencies and pipeline hazards.

Constraint Random Based Verification of 16-bit ALU using System Verilog

Testing of TL-1963A Low dropout regulator March 2017-May 2017

Line Regulation, Load Regulation, Dropout voltage, Input reverse leakage and Reverse output current tests are performed on low dropout regulator using Automated Test Equipment (PXI). Code is written in LabVIEW. Cp and Cpk values are obtained from the test measurements using JMP software

Mixed Signal Characterization and Testing of ADC 7800JU Jan 2017

Validated the functionality of DUT with its datasheet, performed various parametric and functional tests on the Mixed Signal IC on PXIe 1075, and bench equipment.

Developed LabVIEW code and test procedures to test. Performed statistical analysis on the data obtained from ATE and bench equipment for its reliability through process capability parameters such as Cp, Cpk and GRR using JMP software

Design of an assembler for MSP430G2553 instruction set December 2014

Developed code in C++ using Eclipse IDE for a Two pass assembler for MSP430G2553

Supports a set of 32 instructions of MSP430G2553

Design of Firmware for TI DSP board Aug 2017- Dec2017

Developed firmware for TMS320DSK6713 to perform as Equalizer, Filter

Developed BIOS RTOS for the board

Image Processing (Noise Reduction, Edge detection and Object identification) Aug 2016 – Dec 2016

Developed code to read an image using MATLAB and processing it like Noise reduction, Object identification using OpenCL, Message Passing and CUDA scripted in Python

Implementation of Ensemble meta-algorithm Bagging technique based on Support Vector Machine April 2017

Developed code to implement the Bagging technique on a set of data and classify the data using SVM technique



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