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Microsoft Office Engineering

Briarcliff Manor, New York, United States
September 14, 2018

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646-***-**** New York, NY


Pace University, Seidenberg School of Computer Science and Information Systems New York, NY

Master of Science (MS) in Computer Science January 2019

GPA: 3.41

Aurora’s Engineering College Bhongir, India

Bachelors of Technology (BTech) in Electronics and Communication Engineering May 2016

GPA: 3.8


Software Project Management Cloud Computing Data Mining Pattern Recognition Analysis and Design of Algorithms Software Engineering Database Management Systems Computer Vision Image Processing VLSI Hardware Programming Circuit Design


Computer Languages: C, C++, Java, MATLAB

Hardware Languages: VHDL

Web Development: HTML, JavaScript, SQL

Operating System: Mas OS, Microsoft Windows (Windows XP, Windows 8/8.1, Windows 10)

Software: VMware, Xilinx, TASM, Micro Wind, Microsoft Office (Word, Excel, PowerPoint)


Micro Aneurysms(MA) Detection using Deep Learning (MATLAB) April 2018

Researched on Micro Aneurysms detection using fundus images.

Designed a CNN in MATLAB and trained the system with the image patches from fundus images.

Validated the testing and achieved an accuracy of 90.48%

Speech Recognition using Mel Frequency Ceptrum Coefficient (MFCC) October 2017

Developed a system using Carnegie Mellon University’s Sphinx tool to display subtitles in videos by recognizing real-time speech

Matched phonemes in speech to words in a dictionary utilizing the library functions of Sphinx

Recorded sound files using doc.wav format to train system using Java to convert speech into text

Design of Parallel Multiplier using Hybrid Full Adder May 2016

Collaborated with two students to study Multipliers and Full Adders to design a Braun Multiplier to reduce the running time of a circuit.

Utilized a Transistor Level 4T-XOR gate to reduce the power dissipation, the number of gates used, and to increase the speed of calculation.

Designed the circuit in Micro Wind using Complementary Metal Oxide Semiconductors (CMOS) circuits to obtain simulation results using the VHDL codes in Field Programmable Gate Array (FPGA).

Designed and ran a program in a software system to observe simulation results and calculate power dissipation of the circuit


Received a Merit level certificate in a National level Technical Fest Electropedia. September 2014


Workshop, Aurdinobotics conducted by Thinnk Ware, Participant September 2015

Workshop, Quadcoptor conducted by Roboversity. Participant March 2015

National level Cultural Fest, PALLAVI 2K14, Volunteer October 2014


Travelling, Singing, Listening to music

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