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Physical Design Engineer

College Station, Texas, United States
April 09, 2018

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Praneet Bhatia

College Station, Texas *****979-***-**** •


Accomplished professional pursuing an M.S. in Computer Engineering, ready to take the next career step in Verification and Physical Design.

● Digital VLSI Systems Design: Expertise in the development of large-scale integrated circuits combining thousands of transistors into a single chip. Experienced in full-cycle development functions, from design through verification and testing.

● Product Optimization: Demonstrated devotion to producing the most efficient processing systems. Created a modern low offset sense amplifier at the Indian Institute of Technology that beat an MIT produced model’s power delay by 82%.

● Key Strengths: Outstanding work ethic with the proven ability to meet project objectives working both independently and as a member of a team. Finely tuned critical thinking skills honed through years of academic and professional experience.

Core Technologies:

Hardware: Integrated Circuits, Semiconductors, Field Programmable Gate Arrays (FPGA) Applications: MATLAB, Vivado, Cadence, ZSim: SPEC CPU2006 & PARSEC Benchmark, Synopsys Design Vision, Synopsys Primetime

Languages: C++, Python, Verilog


Master of Science in Computer Engineering – expected 2018 Texas A&M University, College Station, TX • GPA 3.6/4.0 Key Coursework: Advanced VLSI Logic Synthesis, Digital Integrated Circuit Design, Computer Architecture Bachelor of Engineering (Honours) in Electrical and Electronics Engineering – 2015 Birla Institute of Technology and Science (BITS), Goa, India • GPA 3.6/4.0 EXPERIENCE HIGHLIGHTS

Indian Institute of Technology, Indore, India

Research Engineer, 1 2/2014 – 02/2016

Technologies: U MC 65nm, gpdk 45nm libraries

Executed the full-cycle design and implementation of sense amplifiers for high speed SRAMs. Applied novel dynamic resistance states concepts to analyze the mechanisms responsible for sensing, failure, and corrective actions.

Produced a modern low offset alternative with an 82% lower power delay than a different low offset alternative created by scholars at MIT.


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Praneet Bhatia


Computer Architecture Project, 2 017

Technologies: SPEC CPU2006, PARSEC Benchmark, ZSim Applied Tree-LRU algorithms to create an optimized Minimal Disturbance Placement and Promotion (MDPP) CPU cache replacement policy on ZSim. Analyzed the relationship/performance of LRU, LFU, and SRRIP for both the CPU and the CMP benchmarks.

Microprocessor Systems Design Lab Project, 2 017

Technologies: FPGA, Vivado

Implemented an IR-remote demodulating hardware. Improved the accessibility of messages software by encapsulating the demodulation within a customized IP peripheral. Polled the peripheral registers by designing a IR-remote interfaced application; ultimately avoided the need to poll registers by including an interrupt handling logic.

Digital Integrated Circuit Design Lab Project, 2 017 Technologies: RTL, Verilog, Synopsys Design Vision; Synopsys Primetime, Cadence SoC Encounter Designed and tested the RTL of a cruise-control system in Verilog. Used Design Vision to synthesize the design and Primetime to analyze the pre-layout static timing. Used SoC Encounter to automatically place and route the generated netlist.

VLSI Circuit Design Lab Project, 2 016

Technologies: C adence Virtuoso

Created an Operational Amplifier to generate an output potential exponentially larger than the potential difference between input terminals; ultimately produced a gain of 91.5 dB, GBW of 3.6MHz, and slew rate of 1.4V/us.

Advanced VLSI Logic Synthesis Project, 2 018 (Ongoing) Technologies: C, Python, Verilog, FPGA, SPICE

Develop a hardware engine for a CNN and a corresponding software simulator. VLSI Machine Learning Systems Project, 2 018 (Ongoing) Technologies: Python, Verilog, FPGA

Develop a computer vision system for handwritten digit recognition. PUBLICATIONS

1. An offset-tolerant self-correcting sense amplifier for robust high speed SRAM, P. Bhatia, B. S. Reniwal and S. K. Vishvakarma, 19th International Symposium on VLSI Design and Test, Ahmedabad, 2015. 2. Design and investigation of variability aware sense amplifier for low power, high speed SRAM, B.S. Reniwal, P. Bhatia, S.K. Vishvakarma, Microelectronics Journal, Volume 59, January 2017.

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