Sign in

Electrical Engineering Manager

Plano, Texas, United States
January 15, 2018

Contact this candidate


Junyu Lu

Plano, TX, ***** 214-***-****


Actively seeking for a full-time job in Electrical Engineering


The University of Texas at Dallas, Richardson, Texas May 2017

MSEE. GPA: 3.393

South China Normal University, China July 2015

BS in Communication Engineering. GPA: 3.05


Languages: Verilog, Python, VHDL, C, C++, PL/SQL, PHP

Operating Systems: UNIX, Windows (all versions)

Software: Modelsim, Visual Studio, Quartus, Cadence, Synopsys, SQL developer, MS office, MATLAB


Junior Engineer 11/2017-

Neosen Energy, Plano, TX

• Assisted in embedded programming for different project, including library, main code and performed testing

• Currently working on battery test with STM32 and Temperature and humidity sensor Si7021

Intern 07/2014-09/2014

Network Maintenance Department, China Unicom

• Instructed by the manager and aided in business negotiation, on-spot investigation for base station construction, and the construction progress supervision

• Designed the official account in WeChat


ASIC Design

• Designed a Mini Stereo Digital Audio Processor (MSDAP) in Verilog

• Designed a Finite State Machine (FSM) to control MSDAP. Defined all the I/O pins and FSM states.

• Designed the architecture of MSDAP in RTL, verified gate-level netlist using Modelsim

• Performed floorplanning, clock tree synthesis (CTS), static timing analysis (STA), placement and routing to generate layout using Synopsys IC Compiler

VLSI Design

• Designed a 20-bit Calculator with Verilog, using own library with Cadence and Synopsys tools

• Designed a basic cell library with drawing the schematic and layout of INV, NAND2, NOR2, XOR3, MUX2_1, OAI3221, AOI22, and D flip-flop. Ran simulation with DRC, QRC and LVS in Cadence environment

• Obtained worst case delay by analyzing STA with Primetime. Placement and routing were done by Candance Encounter.

FPGA Design

• Used Quartus to design a digital coded lock in VHDL with an FPGA chip

• Realized the coded lock with 4 functions: verification, alarm system, resetting and changing combination

• Used frequency sweeping to implement the 4-digit display, and eliminated dither for the buttons.

Queuing Network Design

• Implemented a simulation using C++ for a queuing network with two classes of customers and two queues, measured the performance of the network based on simulation results with theoretical data.

Contact this candidate