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Engineer Test

Hillsboro, Oregon, United States
January 15, 2018

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Nathaniel Jarpa

**** ** ********* ****** *********, OR 97123. Tel: 503-***-****

Personal Statement

Experienced IT/Software Validation Engineer with over 12 years of combined experience is seeking a position with a company where my knowledge and skills can be utilized.

Work Experience

Protingent/Microsoft - IQA Surface Hub 5/2016 -10/2017

•Configured computer systems with newer BIOS/Firmware, TPM, and wireless drivers

•Ran Pass Mark BurnInTest utility to test CPU, 2D/3D graphic, memory, and playback video

•Tested wireless drivers

•Tested cameras

•Helped the manufacturing floor to debug Bios/firmware and TPM issues

•Performed inspection on incoming parts including chassis, motherboards, and video boards

•Compiled daily work summary report for supervisor/lead

•Repaired test equipment when needed and assisted to organize work at the start

NetPolarity/Intel Corporation - Cloud Systems Engineer 4/2015 – 7/2015

Assembled servers with needed hardware (SSD, SATA SAS, DDR3 or DDR4, PCIE) based on customer’s order and performed QA test to meet requirements

Developed testing methodology for embedded systems

Updated systems with new firmware/BIOS and verified system functionality

Validated CentOS 7.1 or Windows 2012 R2, configurations and load Intel Media Server Studio,

Configure RAID on systems with SAS drive and made sure RAID functions as expected

Setup proxy server, configured network on the system and performed functional test to make sure it acts as expected

Configured systems using Python to debug drivers and utilities with Linux based OS

Troubleshoot systems errors, file bugs, and tracked all bugs in Jira or HSD for prompt resolution

Configured RDP or VNC for remote testing and installation of utilities for customers ‘support

Performed verification and validation on systems prior to shipping to customers

Experienced with benchmark testing

Randstad/Intel System Integration Engineer III – Intel 11/2013 to 07/2014

Worked on engineering conceptual demos that include board level and software integration.

Loaded Linux or Windows operating system as needed during testing

Validated Windows and Linux operating systems

Upgraded systems with newer firmware and BMC

Performed and documented power management procedures for business continuity

Build network infrastructure to enable OEMS to perform remote testing of applications off site

Integrate and configure servers with Linux operating systems

Tested CLST throttling on OEMs systems and also participated in meetings to demo CLST

Validation Lead May-2010 - Aug-2012

Intel Corporation, Hillsboro, Oregon

Worked with complex BIOS vendors validation programs, facilitating the resolution of bugs by working with developers

Designed specifications and developed methodology on reporting defects and other work-related issues to Intel representative for smooth operation

Developed BIOS validation strategy and planning documents with developers to be used by vendors.

Streamlined and enhanced the system validation process for BIOS vendors to meet Intel standard and expectations

Developed test plans and test cases to focus on specific tasks related to assigned project

Developed test plans for embedded systems such as NAND technologies

Successfully transitioned low level validation tasks to India, monitored, trained, and supervised new validation engineers in India for successful takeover of tasks

Validation lead for validation contractors work schedule, trained, and mentored each contractor on validation procedures for all projects

Worked on planning and development of testing BIOS security technology (PFAT)

Participated in power-on process of new mother boards and CPU at Intel

Intel Corporation, Hillsboro, Oregon Apr-2008 - Apr-2010

Worked on TDT (Theft Deterrent Technology) security test development and testing with success to technology launch

Validated TPM (Trusted Platform Module) security features to meet BIOS requirement

Performed CIRA (Client Initiated Remote Administration) network technology to a successful launch

Worked on SFF (small form factor) ERBs Fern Hill, Golconda Summit to project launch

Validated WIFI/WIMAX Wireless Technology to program successful launch

Integration and Validation Engineer Intel Corporation, Hillsboro, Oregon May-2005 - Mar-2008

Validated Active Management Technology to verify AMI, Phoenix and Tiano BIOS support AMT.

Setup Intel Mobile computer hardware on testing platforms, i.e. latest motherboard, CPU, memory, IDE/SATA hard drives etc.

Custom built and configured released and engineering test BIOS/AMT images using software programming tools.

Flashed SPI and firmware using software and external DediProg serial flash programming tool.

Ran various hardware stress and BIOS/AMT test scripts and applications. Tested AMT client/server functionality and performance test over LAN and wireless connected networks. Recorded all results in an excel test procedure document.

Reported and tracked all bugs using Intel bug tracking software, worked with engineers to help troubleshoot and resolve hardware/software issues.

Performed board rework, used DMM, Oscilloscope, soldering equipment and various tools.

Followed documented procedures, trained new technicians and participated in team meetings.

Engineering Technician Intel Corporation, Chandler, AZ Jan-2000 - Apr-2005

Consolidated 21 ATD Automation Client Engineering cases into IT solution database to streamline system reference

Assisted on Station Controller binders update and optimization by moving all files to their appreciate drives

Worked in a team to modify Dual Core POR U-clips for IHS Module Engineering

Qualified JEDEC UHT 42.5 FCBGA5 trays through oven at Ball Attach and performed data analysis for module engineer for risk assessment

Performed technical tests and experiments in wafers fabrication environment and helped to modify equipment and/or processes to improve yield results. Worked in cleanroom environment for over 3 years using testing tools (KLM) to identify defects Trained technicians on how to Defect Metrology tools such as CIA, (Cassette Integrity Automation). XRFC, SEM/EDX, Klarity, and SPC


Master’s Degree, Portland State University 2009

BSC’ University of Phoenix 2003

AA CHI Institute 2000


Experienced working in SDLC, Agile testing, bug tracking, user acceptance testing, and defect tracking tool

Test plan development for new products, Failure analysis, debugging, and strong analytical skills

Testing/verification skills, team player, customers relations, excellent problem-solving skills

Project Management skill and training

Strong initiatives, a self-starter, and the ability to multitask with excellent experience in cross-team interaction.

Sound knowledge in software testing processes and methodologies

Computer Languages: C#, C++, Java, Python

Communicate well, discipline, honest, and hardworking

Operating systems: Windows, Linux, and Android.

Experienced working with I/O Devices, PCI Devices, PCI-E Devices, NAND technologies, Hard Drives (PATA & SATA), USB, DDR3, DDR3L, & USB

Test tools Oscilloscope, logic analyzer, digital multi-meter, function generator

Experienced with BIOS, firmware, and drivers test development and test execution

Experienced validating WIMAX modules and drivers


Received recognitions from cross teams

Received kudos valued over $550 for outstanding performance


References Available on Request

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