| Resume alert | Resumes 21 - 30 of 233 |
Project Assistant
New Delhi, Delhi, India
... Summer Training: • VHDL of 4 weeks of my 4 th sem in CETPA. • MATLAB of 45 Hour BIT,Gorakhpur in CETPA. • Core java training of 45 Hour BIT,Gorakhpur in CETPA. • C Language 2 weeks of my 7 thsem of LTB. • Embedded Systems 4 weeks of my 6 thsem in ... - 2020 Jan 20
... Summer Training: • VHDL of 4 weeks of my 4 th sem in CETPA. • MATLAB of 45 Hour BIT,Gorakhpur in CETPA. • Core java training of 45 Hour BIT,Gorakhpur in CETPA. • C Language 2 weeks of my 7 thsem of LTB. • Embedded Systems 4 weeks of my 6 thsem in ... - 2020 Jan 20
Engineer Design
Noida, Uttar Pradesh, India
... and PIR sensor ● Telegram Messenger Service Technical Skills Programming languages ● C ● Embedded C ● Python (Beginner) ● VHDL Softwares ● Arduino IDE ● TRUE STUDIO ● Atmel Studio 6.2 ● KiCAD ● Eagle ● MATLAB ● XILINX ISE 10.1 Microcontrollers ● ... - 2019 Oct 13
... and PIR sensor ● Telegram Messenger Service Technical Skills Programming languages ● C ● Embedded C ● Python (Beginner) ● VHDL Softwares ● Arduino IDE ● TRUE STUDIO ● Atmel Studio 6.2 ● KiCAD ● Eagle ● MATLAB ● XILINX ISE 10.1 Microcontrollers ● ... - 2019 Oct 13
Design Engineer Project
New Delhi, Delhi, India
... Software : Tanner EDA, XILINX, FTA CDU, ModelSim Familiar Concepts : Digital Electronics, Network Analysis, CMOS Design Languages : Verilog, System Verilog, Basic of C Programming, VHDL ACHIEVEMENTS • Qualified GATE 2017 ECE with score 522. ... - 2019 Oct 04
... Software : Tanner EDA, XILINX, FTA CDU, ModelSim Familiar Concepts : Digital Electronics, Network Analysis, CMOS Design Languages : Verilog, System Verilog, Basic of C Programming, VHDL ACHIEVEMENTS • Qualified GATE 2017 ECE with score 522. ... - 2019 Oct 04
Engineer Microsoft Office
New Delhi, Delhi, India
... 10th C.B.S.E 2004 47.6% Technical Skills: Course on Computer Concepts (CCC Certificate) from NIELIT C & C++ VLSI ( Verilog,VHDL) Microsoft Office including word, power point, excel etc. Hobbies: 1.Internet surfing 2.Reading newspaper 3.Visiting ... - 2019 Jul 29
... 10th C.B.S.E 2004 47.6% Technical Skills: Course on Computer Concepts (CCC Certificate) from NIELIT C & C++ VLSI ( Verilog,VHDL) Microsoft Office including word, power point, excel etc. Hobbies: 1.Internet surfing 2.Reading newspaper 3.Visiting ... - 2019 Jul 29
Physics Faculty
Noida, Uttar Pradesh, India
... TECHNICAL SKILLS: Fields of Interest : IB Physics, Semiconductor, VLSI, Digital Electronics Languages Known : C, C++, Python, and Perl FPGA : VHDL and Verilog Design Tools : MATLAB, Virtuoso, Xilinx, Keil, LTspice, Eldo Degree University/Board ... - 2019 Jun 24
... TECHNICAL SKILLS: Fields of Interest : IB Physics, Semiconductor, VLSI, Digital Electronics Languages Known : C, C++, Python, and Perl FPGA : VHDL and Verilog Design Tools : MATLAB, Virtuoso, Xilinx, Keil, LTspice, Eldo Degree University/Board ... - 2019 Jun 24
Professor
New Delhi, Delhi, India
... Languages C, VHDL, Verilog. PUBLICATIONS (INTERNATIONAL JOURNALS) 1.Research paper published in Journal of Mechanics of Continua and Mathematical Sciences 2019 vol. 14(1) page 414-421 on “Sensitivity enhancement and comparison of MEMS/NEMS ... - 2019 Jun 05
... Languages C, VHDL, Verilog. PUBLICATIONS (INTERNATIONAL JOURNALS) 1.Research paper published in Journal of Mechanics of Continua and Mathematical Sciences 2019 vol. 14(1) page 414-421 on “Sensitivity enhancement and comparison of MEMS/NEMS ... - 2019 Jun 05
Summer Training Data Entry
Noida, Uttar Pradesh, India
... Public School, Agra (U.P.) 2006 55.60% CBSE, (10th ) Central Public School, Chapra (Bihar) 2004 70.06% Certificate courses: VHDL programming language Extra-Curricular Activities: Served as Branch Coordinator the Annual fest ELECTROSPECTRUM 2009 & ... - 2019 Apr 15
... Public School, Agra (U.P.) 2006 55.60% CBSE, (10th ) Central Public School, Chapra (Bihar) 2004 70.06% Certificate courses: VHDL programming language Extra-Curricular Activities: Served as Branch Coordinator the Annual fest ELECTROSPECTRUM 2009 & ... - 2019 Apr 15
Test Cases
New Delhi, Delhi, India
Resume Area of Expertise Verilog, VHDL, System Verilog, perl, C, UVM Work Experience ● 11 yrs in Product Validation at Cadence as Lead Product Validation Engineer. Project Details (Feature testing of Xcelium from Oct, 2015 till March, 2019) 1. ... - 2019 Apr 12
Resume Area of Expertise Verilog, VHDL, System Verilog, perl, C, UVM Work Experience ● 11 yrs in Product Validation at Cadence as Lead Product Validation Engineer. Project Details (Feature testing of Xcelium from Oct, 2015 till March, 2019) 1. ... - 2019 Apr 12
English Teacher Summer Training
New Delhi, Delhi, India
... System 8 Week Summer training in MTNL on Switching System Academic Project Major project on Robotic Arm Implementation using VHDL Programming Extra Curricular Activities Won second prize at intercollegiate tech event in model presentation Organizing ... - 2018 Sep 13
... System 8 Week Summer training in MTNL on Switching System Academic Project Major project on Robotic Arm Implementation using VHDL Programming Extra Curricular Activities Won second prize at intercollegiate tech event in model presentation Organizing ... - 2018 Sep 13
Project Engineering
Delhi, India
... Six week summer Internship at Thapar University during June-July 2013 covering Micro controller, PCB Fabrication,VHDL and Orcad software. 2. Design Astable and Monostable Multivibrator (Minor project at college). TECHNICAL SKILLS Software Languages ... - 2018 Aug 09
... Six week summer Internship at Thapar University during June-July 2013 covering Micro controller, PCB Fabrication,VHDL and Orcad software. 2. Design Astable and Monostable Multivibrator (Minor project at college). TECHNICAL SKILLS Software Languages ... - 2018 Aug 09