Resume

Area of Expertise

Verilog, VHDL, System Verilog, perl, C, UVM

Work Experience

● 11 yrs in Product Validation at Cadence as Lead Product Validation Engineer. Project Details

(Feature testing of Xcelium from Oct, 2015 till March, 2019) 1. Validation of various simulation features e.g.

● Validate/Debug X-prop using simcompare.

To detect propagation of X’s in the customer design & check it’s validity by looking at the values of all signals contributing to the signal’s which are carrying X. Comparison of SHM database was also done to check the X generation using simcompare.to help customer resolve X-propagation issues via webex or report to RD on issues found during validation. SOC validation : NXP, fujitsu, Imagination, Samsung & NY. IP validation : PCIE, AXI3,AXI4,USB2.0.

● Incremental Elab

To test the Auto Multi Snapshot Incremental Elab feature of Xcelium by running the customer design on performance machines & compare the numbers with monolithic design.

Run the design along with UVM environment & check functionality and performance of MSIE with monolithic flow.

● All access modes with numerous perf options

1. To test new constraint solvers with various performance optimizations done by RD by creating test in Systemverilog class based environment & importing OVM/UVM packages.

2. To test the same environment with various access modes along with the new constraint solvers developed by R&D.

3. To test performance feature in which reg were considered as wire in case there was no memory to boost performance of Cadence tools. Test were written in SV & verilog to check any change in behaviour and also on customer chamber test using SHM dumping & performance measurement on performance machines.

● Shm DB dumping (multi-core as well as multi-thread dumping) To generate SHM database by running customer test on single core & re-running the design on multi-core and comparing DB, performance and profiler reports. If there are any issues then report to RD.

● Profiler for Sim time & memory

To validate xprof and old profiler xmprof by running class based environment test with iprof and validate the DB generated for any incorrect data. 2. Support for relational operators,strings for osvvm in vhdl To create test in VHDL to check support for relational operators of different datatypes e.g. unsigned,std_logic_vector,real, signed int around relational operators to follow OSVVM features.

To create test in VHDL for support added for vhdl data type Strings for OSVVM. 3. Creating test for new features added for simulation. E.g. libcache In case where generated snapshot is huge & is kept over a network. Then compile time increases tremendously for over the network access of snapshot. I created test in SV to check the new feature libcache in which snapshot was copied to local disk & check it’s validity using simulation SHM db. From Jan 2012 till July 2015 (Profiler)

1. Joined Sim profiler team to test new tool Iprof by writing test in verilog, VHDL, SV, DPI, VPI & their combinations.

Initially RD created a batch profiler in which text based report was generated on Callgraphs.

I created test in SV/UVM to check the validity of reports generated by profiler tool Iprof Callgraphs were generated using connecting SV class methods and UVM methods with DPI,VPI interface’s.

2. Created perl scripts to measure performance of the new profiler Created perl scripts to extract data from Profiler reports & goldanise to run them in nightly regression.

3. Wrote gui test in Specman E to test gui interface of sim profiler & created perl scripts to check gui performance for smooth integration of Specman with Iprof. Gui was tested by me by creating test cases in E using in house tool gtx. From June 2009 to Dec 2011(Project HAL)

1. Joined HAL team to deliver HAL rules around SV interface, Lint/synth pragma, protected Code, Casex & Casez.

Created test in SV interface and added pragma to check correct reporting of rules by tool HAL

2. Created more customised rules for HAL in C using API Created test in C to check HAL for customized rules feature of HAL 3. Generated code coverage numbers for HAL which helps RD remove dead code & PV to add more test.

Ran code coverage gcov to generate line & functional coverage numbers for HAL. If coverage was lacking then i wrote test in SV/verilog/VHDL to improve coverage. 4. Joined Sim PV to look for performance degradation by analysing nightly failures To check for any performance degradation on customer benchmark test running daily. 5. To test Specman E checks through HAL

Wrote test in E to check integration of Specman with HAL. Aug 2008 to June 2009(Project VPI/DPI)

Joined SV PV Team for writing VPI test cases in C to test support for 1. logic/bit datatype in SV though VPI.

Created test in C to check VPI support added for logic and bit datatype of SV. 2. To test always_ff & always_latch in SV through VPI Created test in C to test if VPI was providing the right handle to traverse the always_ff and always_latch.

3. Converted Existing pli test to vpi.

Changed all pli test to vpi in C.

4. To test SV DPI support by writing test in DPI . Wrote test cases in SV-DPI to test whether values were transacted smoothly through DPI.

Aug 2007 to July 2008 (Project HAL )

1. Joined RFT in HAL PV to test new rules for HAL in SV/Veriog & VHDL. 2. Delivered Custom rule checks for HAL by writing test in C 3. To Test single verb invocation of HAL though irun. Created test cases in SV,verilog & vhdl to test fujitsu specific design rules around synthesizability rules, Structural rules & naming convention Feb 2006 to Feb 2007 : Internship in Lint checking tool HAL for verification

1. Verified Lint rules by writing test in Verilog/VHDL. Verified HAL rules for Freescale & ST around tasks & functions 2. Created Performance Test Suite using Perl.

Created performance test suite page using cgi-perl and created perl scripts to extract data from log files

3. Created test for all rules of HAL including synthesis & structural checks. Created test in SV and verilog for freescale deliverables around synchronous flops and combinational loop.

Educational qualification

● VLSI training from Vedant, Semiconductor Complex Limited (Mohali, Punjab), 2005

● B.Tech in Electronics & Instrumentation from Technological Institute of textile & sciences,(MDU,Rohtak) 2000-2004

● Hans Raj Model School, New Delhi.

Hobbies

Playing chess & reading latest on technology, current affairs & Jogging. Contact Details:

Aman Chawla

ac82n9@r.postjobfree.com,

626-Vikas Kunj,

Vikas puri,

New Delhi-18

971*******

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