| Resume alert | Resumes 41 - 50 of 202 |
Office Personal
Hyderabad, Telangana, India
... Andhra Pradesh 2014 7.8 (GPA) TECHNICAL Operating System : UNIX Languages known : C Programming, Embeddedsystems, ( knowledge on 8086 MPMC ),VHDL basics Packages : MS office,power point PERSONAL Easy grasping of work with “ can do” attitude. ... - 2020 Apr 04
... Andhra Pradesh 2014 7.8 (GPA) TECHNICAL Operating System : UNIX Languages known : C Programming, Embeddedsystems, ( knowledge on 8086 MPMC ),VHDL basics Packages : MS office,power point PERSONAL Easy grasping of work with “ can do” attitude. ... - 2020 Apr 04
Microsoft Office Engineering
Hyderabad, Telangana, India
... Chaitanya jr.college Vizag 2015 75% SSC Bhashayam Public School Vizag 2013 63% INTERNSHIPS: Internship on ‘VHDL Programming & its basic implementation on FPGA’S’ (DRDO) for a period of four weeks and have designed a project entitled ‘LED BLINKING’. ... - 2020 Feb 16
... Chaitanya jr.college Vizag 2015 75% SSC Bhashayam Public School Vizag 2013 63% INTERNSHIPS: Internship on ‘VHDL Programming & its basic implementation on FPGA’S’ (DRDO) for a period of four weeks and have designed a project entitled ‘LED BLINKING’. ... - 2020 Feb 16
Engineering Technical
Hyderabad, Telangana, India
... Mathews High School 2009 – 2011 Hindi Language Hindi Prachar Sabha-Hyderabad Kazipet Hindi Vidwan Hindi Visharad Hindi Bhushan TECHNICAL SKILLS VHDL(basic), C language(basic), Matlab & Multisim software(basic), Python(basic). Communication Skills ... - 2020 Jan 06
... Mathews High School 2009 – 2011 Hindi Language Hindi Prachar Sabha-Hyderabad Kazipet Hindi Vidwan Hindi Visharad Hindi Bhushan TECHNICAL SKILLS VHDL(basic), C language(basic), Matlab & Multisim software(basic), Python(basic). Communication Skills ... - 2020 Jan 06
Sr. IT Recruiter/ Talent Acquisition/Sourcing/Payroll/HR
Hyderabad, Telangana, India
... Static Timing Analysis, Library Analysis, Analog Layout, Signal Integrity Analysis, Timing Closure, TCL,Tk, Perl, Ruby, Python, Shell, K-Shell, Embedded-C, Assembly-C, C, System C, C++, Java, SOC, UVM, VMM, Verilog, System Verilog, OVM, VHDL. ... - 2020 Jan 06
... Static Timing Analysis, Library Analysis, Analog Layout, Signal Integrity Analysis, Timing Closure, TCL,Tk, Perl, Ruby, Python, Shell, K-Shell, Embedded-C, Assembly-C, C, System C, C++, Java, SOC, UVM, VMM, Verilog, System Verilog, OVM, VHDL. ... - 2020 Jan 06
Fresher(B.Tech -ECE)
Hyderabad, Telangana, India
... Voter id Participated in Hackathon under Telangana Smart City: Automatic Temperature and Humidity Control using IOT Student of Cisco Networking Academy and member of IEEE, IETE Professional Highlights: Languages: VHDL, Verilog, C Language. ... - 2020 Jan 04
... Voter id Participated in Hackathon under Telangana Smart City: Automatic Temperature and Humidity Control using IOT Student of Cisco Networking Academy and member of IEEE, IETE Professional Highlights: Languages: VHDL, Verilog, C Language. ... - 2020 Jan 04
Design Engineer Assistant
Malkajgiri, Telangana, India
... Languages and Tools Hardware Languages :- Verilog HDL, VHDL Scripting Languages :- Linux Shell Scripting, Introduction to Perl, TCL Software Languages :- C, C++, MATLAB Hardware Description Languages & Associated Tools: Xilinx ISE, Questa-Sim, Model ... - 2019 Dec 27
... Languages and Tools Hardware Languages :- Verilog HDL, VHDL Scripting Languages :- Linux Shell Scripting, Introduction to Perl, TCL Software Languages :- C, C++, MATLAB Hardware Description Languages & Associated Tools: Xilinx ISE, Questa-Sim, Model ... - 2019 Dec 27
Team Leader Power
Hyderabad, Telangana, India
... GT-DESGINER,MITSUBISHI Designed and programmed a Power Strapping Feeder Machine using CAD (ELECTRICAL – 2013) Languages C, C++, VHDL Software MATLAB,PSPICE,PLC,AUTOCAD,EPLAN,HMI,XILINX Applications MS Office Operating Systems Windows XP / Windows7 ... - 2019 Dec 26
... GT-DESGINER,MITSUBISHI Designed and programmed a Power Strapping Feeder Machine using CAD (ELECTRICAL – 2013) Languages C, C++, VHDL Software MATLAB,PSPICE,PLC,AUTOCAD,EPLAN,HMI,XILINX Applications MS Office Operating Systems Windows XP / Windows7 ... - 2019 Dec 26
Industrial Training Engineer
Hyderabad, Telangana, India
... Packages : VHDL Module,Multisim. Operating systems : WINDOWS Variants. INDUSTRIAL TRAINING PROGRAM: Have been completed my industrial training program on ‘DELTA PAPER MILLS LTD’ Vendra,Palakoderumandalm,West Godavari district,A.P..for a six months ... - 2019 Dec 17
... Packages : VHDL Module,Multisim. Operating systems : WINDOWS Variants. INDUSTRIAL TRAINING PROGRAM: Have been completed my industrial training program on ‘DELTA PAPER MILLS LTD’ Vendra,Palakoderumandalm,West Godavari district,A.P..for a six months ... - 2019 Dec 17
Power Training
Hyderabad, Telangana, India
... Previous Employer : Capitalaim Financial Advisory INDIA PVT LTD Designation : Executive Trainee Tenure in months : Oct 2018 to Mar 2019 Technical Skills: Programming languages C, C++, Core Java Assembly languages 8085,8086 and 8051 VLSI (VHDL coding ... - 2019 Dec 11
... Previous Employer : Capitalaim Financial Advisory INDIA PVT LTD Designation : Executive Trainee Tenure in months : Oct 2018 to Mar 2019 Technical Skills: Programming languages C, C++, Core Java Assembly languages 8085,8086 and 8051 VLSI (VHDL coding ... - 2019 Dec 11
Engineer Machine
Hyderabad, Telangana, India
... SRI NALANDA JUNOR COLLEGE,RAJAMPET STATE BOARD OF A.P 2009-2011 84.8% SECONDARY SCHOOL EDUCATION INFANT JESUS HIGH SCHOOL, RAJAMPET STATE BOARD OF A.P 1998-2009 77% TECHNICAL SKILLS HARDWARE LANGUAGES: VERIOG HDL, VHDL, MATLAB,MULTISIM,XILINX. ... - 2019 Nov 09
... SRI NALANDA JUNOR COLLEGE,RAJAMPET STATE BOARD OF A.P 2009-2011 84.8% SECONDARY SCHOOL EDUCATION INFANT JESUS HIGH SCHOOL, RAJAMPET STATE BOARD OF A.P 1998-2009 77% TECHNICAL SKILLS HARDWARE LANGUAGES: VERIOG HDL, VHDL, MATLAB,MULTISIM,XILINX. ... - 2019 Nov 09