| Resume alert | Resumes 71 - 80 of 85 |
Engineering Software
Toronto, ON, Canada
... in Engineering Science Computer Option TECHNICAL C/C++, Java, Perl, Python, Verilog, HTML, Quartus II, MS Office Suite, SKILLS Adobe Photoshop, Android OS, W indows 2000/XP/7, UNIX, Linux ENGINEERING Software Engineering Intern at Google Inc. ... - 2013 Jan 27
... in Engineering Science Computer Option TECHNICAL C/C++, Java, Perl, Python, Verilog, HTML, Quartus II, MS Office Suite, SKILLS Adobe Photoshop, Android OS, W indows 2000/XP/7, UNIX, Linux ENGINEERING Software Engineering Intern at Google Inc. ... - 2013 Jan 27
Developer System
Vaughan, ON, Canada
... Skills Web Languages: PHP, Ajax, CSS, HTML, XML, JavaScript, Jquery Programming Languages: C/C++, Java, Visual Basic 6.0, VHDL, Verilog, Assembly Language Operating Systems: Windows XP/98, Vista/7, Ubuntu, Databases: MySQL, PostgreSql,SQL Server, ... - 2013 Jan 24
... Skills Web Languages: PHP, Ajax, CSS, HTML, XML, JavaScript, Jquery Programming Languages: C/C++, Java, Visual Basic 6.0, VHDL, Verilog, Assembly Language Operating Systems: Windows XP/98, Vista/7, Ubuntu, Databases: MySQL, PostgreSql,SQL Server, ... - 2013 Jan 24
Engineer Active Directory
Brampton, ON, Canada
... Wordpress, joomla and windows server 2008 Active directory TelecommunicationH.322, Communications Systems, SIP, HDL using Verilog, Simulating wireless propagation models using MATLAB and booth algorithm using Assembly languageBasic Principles of ... - 2013 Jan 24
... Wordpress, joomla and windows server 2008 Active directory TelecommunicationH.322, Communications Systems, SIP, HDL using Verilog, Simulating wireless propagation models using MATLAB and booth algorithm using Assembly languageBasic Principles of ... - 2013 Jan 24
Engineer Design
Oakville, ON, Canada
... Certificate for School Topper in Class X (Central Board of Secondary Education) April 2000 - March 2001 TECHNICAL SKILLS Technology and CONCEPTS: VLSI: ASIC Flow, Verilog, PCB Schematic - Layout design, PCB Placement and Routing; Networking and ... - 2013 Jan 01
... Certificate for School Topper in Class X (Central Board of Secondary Education) April 2000 - March 2001 TECHNICAL SKILLS Technology and CONCEPTS: VLSI: ASIC Flow, Verilog, PCB Schematic - Layout design, PCB Placement and Routing; Networking and ... - 2013 Jan 01
Engineer Design
Toronto, ON, Canada
... SKILLS Skill Skill Level Experience Design RTL with VHDL, Verilog Expert Currently used 15 years exp. Design Logic in digital circuit Expert Currently used 15 years exp. Simulation with Mentor ModelSim, Cadence Expert Currently used 15 years exp. ... - 2012 Dec 06
... SKILLS Skill Skill Level Experience Design RTL with VHDL, Verilog Expert Currently used 15 years exp. Design Logic in digital circuit Expert Currently used 15 years exp. Simulation with Mentor ModelSim, Cadence Expert Currently used 15 years exp. ... - 2012 Dec 06
Signal Processing Assistant
Toronto, ON, Canada
... TECHNICAL SKILLS MATLAB, C, LaTeX, Assembly, Verilog - 2012 Nov 23
... TECHNICAL SKILLS MATLAB, C, LaTeX, Assembly, Verilog - 2012 Nov 23
Electrical Years Experience
Toronto, ON, Canada
... & SIMULATION SKILLS: 3 years experience Verilog/VHDL design, Altera Quartus II (TimeQuest for timing analysis), and Xilinx ISE Mentor Graphics ModelSim for FPGA simulation and verification Cadence Allegro to review and debug PCB designs MATLAB, ... - 2012 Nov 21
... & SIMULATION SKILLS: 3 years experience Verilog/VHDL design, Altera Quartus II (TimeQuest for timing analysis), and Xilinx ISE Mentor Graphics ModelSim for FPGA simulation and verification Cadence Allegro to review and debug PCB designs MATLAB, ... - 2012 Nov 21
Design Engineering
Toronto, ON, Canada
... SKILLS C, C++, Python, Java PHP, Perl, PHP, Csh/Sh/Bash Programming: Verilog, SPICE Simulation, FPGA and standard cell design Digital Electronics: Design for Power (DFP), Timing analysis/closure Physical Design: Debuggers, Subversion, Git, Doxygen, ... - 2012 Nov 16
... SKILLS C, C++, Python, Java PHP, Perl, PHP, Csh/Sh/Bash Programming: Verilog, SPICE Simulation, FPGA and standard cell design Digital Electronics: Design for Power (DFP), Timing analysis/closure Physical Design: Debuggers, Subversion, Git, Doxygen, ... - 2012 Nov 16
Engineer Electrical
Markham, ON, Canada
... I was also responsible for generating ATPG patterns that passed functional test in Verilog. I have worked on various stages of the design flow and have performed functions such as RTL logic design using Verilog; design verification; Dynamic timing ... - 2012 Oct 11
... I was also responsible for generating ATPG patterns that passed functional test in Verilog. I have worked on various stages of the design flow and have performed functions such as RTL logic design using Verilog; design verification; Dynamic timing ... - 2012 Oct 11
Electrical Engineer Design
Toronto, ON, Canada
... * Verilog and VHDL. * Zuken and Protel schematics capture and PCB layout. * Eagleware. * Xilinx FPGA/CPLD Development tools (ISE6). * ModelSim XE5.6. * MPLAB IDE v6.6. Proficient with the following Bus and Standards: * PCI, ISA, USB, RS-232, RS-485 ... - 2012 Oct 11
... * Verilog and VHDL. * Zuken and Protel schematics capture and PCB layout. * Eagleware. * Xilinx FPGA/CPLD Development tools (ISE6). * ModelSim XE5.6. * MPLAB IDE v6.6. Proficient with the following Bus and Standards: * PCI, ISA, USB, RS-232, RS-485 ... - 2012 Oct 11