Engineer Design
Resume:
Tannu Sharma
Senior
Application Engineer at Cadence Design
Systems
Tannu
Sharma
E-mail: abp5xb@r.postjobfree.com
EDUCATION
Masters of Sciences in Electronics
July 2006 - Jun
2008
Department
of Electronics Science, South Campus, University of Delhi, Delhi
(73.14 %)
Bachelors of Sciences in
Electronics
July 2003 - Jun
2006
Deen
Dayal Upadhyay College, University of Delhi, Delhi (72
%) (College topper: July 2005 - June
2006)
PROFESSIONAL EXPERIENCE
Senior Application Engineer,Cadence Design
Systems (I)
July 2008 - Present
Member
of the Silicon Package Board (SPB) Team:Researched usability and PCB
design flow issues, Developed solutions to designing challenges
faced within the tool using the PCB circuit design expertise and
knowledge of Cadence PCB tools and design flowsDesigned training material
and examples for users and Marketing, PV and R&D.Collaborated on projects to
test new feature with Designers from companies like Intel, STM etc,
from North America, Europe and Asia Pacific.Collaborated with the
R&D, Product Validation, and Marketing teams to focus on
resolving customer defects and enhancementsDeveloped several prototypes
as a proof of concept for enhancement in software
Intern, Alcatel-Lucent
Jan 2008 - June 2008Designed DWDM Optical
Network for client Shyam Telecom with the Presales
team.Developed a Service Call
Tracker : a Mobile Application (in Java)
Graduate Intern,
Alcatel-Lucent
May 2007 - July 2007Designed Digital Estates for
client StarWood Hotels under the Verticals and Enterprise
department.Studied and explored
upcoming technologies, such as WiMAX, and their
applications.
PROJECT
Application Notes: (A published documentation of
breakthrough in design methodology at Cadence Design
Systems.)
Authored two Major
Application notes on PCB design and technology published on the
Cadence Online Support website.
Technology Solutions: (Documentation of the solution to a
design problem using Cadence tools.)
Authored almost 100
solutions related to Allegro PCB design and Allegro SKILL published
at Cadence Online Support website.
Vapour Deposition technique:
Jan 2008 Feb 2008Study of semiconductor fabrication using thin
film growth
Intelligent Traffic Control System B.Sc.
Project:
July 2005-June
2006
Developed traffic
monitoring device to manage traffic and pedestrian signals
(Microprocessor, Sensors, Serial communication)
AWARDS AND ACHIEVEMENTS
At
Cadence Design Systems:
July 2008
- PresentKnowledge Contribution
Award
for 2Q 2012,
1Q 2012, 2Q 2011 1 Q2011;Knowledge Hall of Fame
Award
4Q 2011,
3Q 2011; Hall of Fame
for 3Q 2012, 2Q'2012, 1Q'2012,
4Q'2011, 3Q 2010; Operational Excellence
award
for 3Q 2012,
2Q'2011, 2Q 2010.Special Recognition
certificate
for active
participation in Social Responsibility sand charity activities
(2008, 2011, 2012).
Certificate for
School Topper in Class X (Central Board of Secondary
Education) April 2000 - March
2001
TECHNICAL SKILLS
Technology and CONCEPTS: VLSI: ASIC Flow, Verilog, PCB
Schematic - Layout design, PCB Placement and Routing;
Networking and communication: DWDM, SDH, WiMAX, GSM, FTTU,
MULTISIM, DSP; Assembly Language: 8085,
8086.
Languages: SKILL, C/C++, Java;
Scripting Language: TCL, SHELL,
Perl
Cadence PCB Tools: Allegro PCB Editor, Allegro
Package Designer, Constraint Manager, PCB Librarian, Allegro Design
Entry HDL, OrCAD Allegro Design Entry CIS, OrCAD
Layout
ADDITIONAL ACTIVITES & SKILLS
Teaching Experience (Aug 2003-09): Professional tutoring
to help high-school students and college undergraduates.
Event Organization and Leadership (July 2006-08):
Facilitated Placement Coordination, Industrial Conferences and
Alumni Meets.
Charitable work (2008-Present): Active volunteer of
Make a child Smile (MACS) foundation at Cadence:
Organized several events for raising funds.
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Location - India
Copyright 2012, All other marks are the
property of their respective owners.
Copyright ©2012, All other marks are the
property of their respective owners.
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