Engineer Design

Jay Sung

Toronto Ontario Canada

*******@*****.***

Home: 905-***-****

Office: 905-***-****

Cell: 647-***-****

OBJECTIVE

To obtain a challenging position at an industry-leading company where I can use over my fifteen years of ASIC & hardware design (FPGA Design) experience to contribute to the success of the team, company and product that I am assigned to.

EXPERIENCE

I have over fifteen years of increasing responsibility in the development of complex ASIC using industry standard tools and hardware design with FPGA on PCB. I launched many ICs & Systems (especially video processing chip & board of wireless communication system) to the market successfully in Samsung. I have introduced a current company’s products (ATE) to Korean company of Samsung and Hynix successfully. I have a lot of experiences from product definition through design to verification. I have the experience to contribute to a technical team as well as mentor entry-level engineers since I’ve completed more than ten projects on schedule and on budget.

2002 ~ Present

KingTiger Technology in Toronto, Ontario Canada

Senior FPGA/ASIC Engineer

Xilinx Kintex7/Virtex7 design for DDR3 Interface up to 1866Mbps.

Altera Stratix5 design for the power measurement control in the Semiconductor ATE.

Signal Integrity Analysis on the Board with FPGA and MCU(Micro Controller Unit) using Graphic User interface software in the Semiconductor Test Equipment.

Testing and Characterization of DUT(DDR3 SDRAM) in the ATE(Automatic Test Equipment).

Developing DDR3 SDRAM Controller up to 1.6 Gbps using SERDES (Serial Deserial) IP.

Developed Xilinx Virtex5 FPGA to capture the Sever/Desktop Mother Board Behavior and

To control DDR2/DDR3 SDRAM at the speed of 1.3 GHz in the DDR2/DDR3 SDRAM test equipment.

Worked on the Characterization of Memory ATE System for LVDS Performance Analysis using Xilinx FPGA Virtex5, Virtex2 Pro.

Worked on the Contact Voltage and Leakage Current Measurement of DUT using Xilinx Spartan3AN, Lattice SC.

BTT (Behavioral Testing Technology) development on the DDR2 SDRAM ATE (Automatic Test Equipment) which was adopted by Samsung.

LVDS Integrity and performance check Logic design to diagnose ATE System.

Worked on DDR2 Driver chip development running at 800 MHz Performance on the Memory Tester that was adopted by Hynix Semiconductor.

Worked on ASIC design for DDR400 SDRAM backup that substitutes defect cells of DDR SDRAM with embedded SRAM on UMC 0.18 micron process. It was emulated with the Xilinx Virtex2 FPGA.

Worked on the video processor for network management to remotely control mission critical servers over a TCP/IP connection.

2001

ATMOS in Ottawa, Canada

Senior IC Design Engineer

Worked on the interface for the company’s high speed embedded DRAM

Macro-cell in NEC 0.15 micron merged logic process.

This design was specified to work at 400 MHz random access speed - the world’s fastest DRAM macro-cell.

1990 ~ 2000

SAMSUNG

Senior ASIC Engineer in R&D Dept of the Visual Media Division

Developed a second-generation format converter (scan converter) IC that functions

PC to TV Scan conversion, Interlace to progressive, 100/120Hz, Scaler, DTV ready,

3 dimensional motion adaptive interpolation, PIP/POP, Field rate conversion.

Gate count: one million gates, system clock=74MHz.

Developed the IC (Gate count: 700K gates, High speed clock) and board related to double image quality improvement processing. This IC was adapted to all Samsung progressive TV of one million volume of a year.

Developed a Digital Convergence hardware with FPGA and implemented to ASIC that was adapted to all Samsung projection TV of 300 thousands volume a year.

Digital Logic Design Engineer (ASIC/FPGA) in Samsung

Samsung Electronics Research Institute in UK

Involved in the project that developed a digital video processing IC.

This project was a conversion of all analog component and IC to digital IC.

Multimedia Lab. Corporate Technical Operations

Developed Format Converter IC and board used in Digital TV that was the first product in the world. Developed a Noise Reduction IC and board used in high quality TV.

Developed Aspect Ratio Converter IC and board used in WIDE TV that was the first product launched market successfully in SAMSUNG.

All of these ICs were verified using FPGA on PCB.

Analog and System Engineer in Samsung

Multimedia Lab. Corporate Technical Operations

Developed Wide Screen TV System using an embedded micro-controller.

Designed a board which is consisted of Tuner, IF module, Color decoder, micro-controller. This was a pioneered product in SAMSUNG.

R&D Dept. Visual Media Division

Developed LCD TV Set that was the first product in SAMSUNG.

SKILLS

Skill Skill Level Experience

Design RTL with VHDL, Verilog Expert Currently used 15 years exp.

Design Logic in digital circuit Expert Currently used 15 years exp.

Simulation with Mentor ModelSim, Cadence Expert Currently used 15 years exp.

Design digital logic with FPGA Expert Currently used 13 years exp.

Standard communication protocols such as USB, I2C, SPI, RS232 currently used 10 years exp.

Verification in PCB Board Expert Currently used 10 years exp.

Design Schematic Capture Expert Currently used 10 years exp.

RTL Synthesis with Synopsys, XST Expert Currently used 10 years exp.

Static Timing Analysis Expert Currently used 12 years exp.

SPICE Intermediate +2 years ago 1 year.

Design Analog Circuit Intermediate +5 years ago 4 years

Education:

Bachelors Science Degree: Electronics Engineering.

Korea University South Korea Seoul

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