| Resume alert | Resumes 51 - 60 of 802 |
Design Engineering
Vasant Nagar, Karnataka, India
... Technical skills: VLSI Domain skills: HDL: Verilog HVL: System Verilog Verification methodology: Coverage driven verification, Assertion based verification TB Methodology: UVM EDA Tools: Questa-Sim – Mentor Graphics Riviera Pro – Aldec ISE - Xilinx ... - 2021 Feb 12
... Technical skills: VLSI Domain skills: HDL: Verilog HVL: System Verilog Verification methodology: Coverage driven verification, Assertion based verification TB Methodology: UVM EDA Tools: Questa-Sim – Mentor Graphics Riviera Pro – Aldec ISE - Xilinx ... - 2021 Feb 12
Design Engineering
Vasant Nagar, Karnataka, India
... • Good hands-on experience in System Verilog,Verilog . • Good hands on Experience in implementing Constraint based Randomised testbenches for Design blocks using EDA tool. • Hands-on experience in UVM . • Exposure with databases using SQL. • ... - 2021 Feb 12
... • Good hands-on experience in System Verilog,Verilog . • Good hands on Experience in implementing Constraint based Randomised testbenches for Design blocks using EDA tool. • Hands-on experience in UVM . • Exposure with databases using SQL. • ... - 2021 Feb 12
Engineering Security
Vasant Nagar, Karnataka, India
... U 7.7 2019 PUC SDM pre university college, Ujire Department of Pre-University Education 84.5 2015 SSLC National high school konandur Karnatka Secondary Education Examination Board 92.32 2013 IT PROFICIENCY Languages C, assembly (embedded), Verilog. ... - 2021 Feb 12
... U 7.7 2019 PUC SDM pre university college, Ujire Department of Pre-University Education 84.5 2015 SSLC National high school konandur Karnatka Secondary Education Examination Board 92.32 2013 IT PROFICIENCY Languages C, assembly (embedded), Verilog. ... - 2021 Feb 12
Design Project
Vasant Nagar, Karnataka, India
... Software: C, C++, Verilog, VHDL, Physical layout, Analog layout, Memory layout Standard Cell layout design, ASIC, LVS, DRC, Embedded C. 2. Software Tools: MATLAB Simulink, Xilinx ISE, Cadence Virtuoso, GLADE, Mentor Graphics, Spice simulation. 3. ... - 2021 Feb 12
... Software: C, C++, Verilog, VHDL, Physical layout, Analog layout, Memory layout Standard Cell layout design, ASIC, LVS, DRC, Embedded C. 2. Software Tools: MATLAB Simulink, Xilinx ISE, Cadence Virtuoso, GLADE, Mentor Graphics, Spice simulation. 3. ... - 2021 Feb 12
Embedded Engineer
Vasant Nagar, Karnataka, India
... analysis and designing (intermediate) Digital circuit analysis and designing (intermediate) PCB design (intermediate) Verilog and VLSI design (intermediate) TOOLS AND TECHNOOGIES STM32CubeIDE, CubeMX, Keil IDE and debugging (intermediate) KiCAD ... - 2021 Feb 12
... analysis and designing (intermediate) Digital circuit analysis and designing (intermediate) PCB design (intermediate) Verilog and VLSI design (intermediate) TOOLS AND TECHNOOGIES STM32CubeIDE, CubeMX, Keil IDE and debugging (intermediate) KiCAD ... - 2021 Feb 12
Design Power
Vasant Nagar, Karnataka, India
... ACADEMIC PROJECTS PROJECT 1 2018-2019 + Title: Design, Verification of Memory IP Core using System Verilog * HDL: Verilog, Tools: Cadence PROJECT 2 2018-2019 * Title: Design, Verification of fifo IP Core using System Verilog * HDL: Verilog, Tools: ... - 2021 Feb 12
... ACADEMIC PROJECTS PROJECT 1 2018-2019 + Title: Design, Verification of Memory IP Core using System Verilog * HDL: Verilog, Tools: Cadence PROJECT 2 2018-2019 * Title: Design, Verification of fifo IP Core using System Verilog * HDL: Verilog, Tools: ... - 2021 Feb 12
Engineer Design
Bangalore, Karnataka, India
... providing exposure to new ideas that stimulates professional and personal growth Skill Set Programming Language : Verilog HDL, System Verilog Verification methodology : UVM Tools : ALDEC Riviera Pro Software skills : Basic of C Platforms : ... - 2021 Feb 09
... providing exposure to new ideas that stimulates professional and personal growth Skill Set Programming Language : Verilog HDL, System Verilog Verification methodology : UVM Tools : ALDEC Riviera Pro Software skills : Basic of C Platforms : ... - 2021 Feb 09
Engineer Engineering
Bangalore, Karnataka, India
SHRUTI SHANKAR CONTACT adj199@r.postjobfree.com 886******* Electronic City, Bangalore SKILLS Software : C, Embedded C Operating system: GPOS(Linux), EOS, RTOS Hardware Description language: System Verilog, Verilog Microprocessor: ARM Cortex M3, ... - 2021 Feb 09
SHRUTI SHANKAR CONTACT adj199@r.postjobfree.com 886******* Electronic City, Bangalore SKILLS Software : C, Embedded C Operating system: GPOS(Linux), EOS, RTOS Hardware Description language: System Verilog, Verilog Microprocessor: ARM Cortex M3, ... - 2021 Feb 09
Quality Engineer Project
Indian Institute of Management Bangalore, Karnataka, India
... Simulators Handled - Spice-simulator, Mat lab, oracle ERP, Xilinx, IT MES suite, BAAN, FLEX-FLOW • Languages - C, C++, VHDL, Verilog, Basics of Java and C#, MS-SQL, Integrator, SQL CORE SKILLS • Manufacturing operations • Hands on experience in IIS, ... - 2021 Feb 09
... Simulators Handled - Spice-simulator, Mat lab, oracle ERP, Xilinx, IT MES suite, BAAN, FLEX-FLOW • Languages - C, C++, VHDL, Verilog, Basics of Java and C#, MS-SQL, Integrator, SQL CORE SKILLS • Manufacturing operations • Hands on experience in IIS, ... - 2021 Feb 09
Engineering Personal
Bangalore, Karnataka, India
... TECHNICAL QUALIFICATION: Area of interest: VLSI Design, FPGA, Embedded Systems, PCB Design Programming and Scripting: Basics of C Programming, Basics of Verilog Simulation tools: Keil, Linux Operating Systems: Red hat, Windows XP/7/8/8.1/10 ACADEMIC ... - 2021 Feb 08
... TECHNICAL QUALIFICATION: Area of interest: VLSI Design, FPGA, Embedded Systems, PCB Design Programming and Scripting: Basics of C Programming, Basics of Verilog Simulation tools: Keil, Linux Operating Systems: Red hat, Windows XP/7/8/8.1/10 ACADEMIC ... - 2021 Feb 08