Verilog resumes in Hosur, Tamil Nadu, India

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c, c++, verilog, vhdl, Cadence

Vasant Nagar, Karnataka, India
... R.T.G High school, Bellary, KA MAR- 2014 Percentage: 85.28%, Distinction SKILLS Programming: C, C++, Oops, DS & Algos,Verilog, VHDL, Assembly language, Python Development Tools: Cadence, Xilinx Vivado, Matlab, simulink, Pspice, CAED using Solid ... - 2021 Feb 15

Digital Engineering

Bangalore, Karnataka, India
... concept and Techniques used in Digital Electronics • Programming Language: C, Python, Assembly languages in 8086, 8051 and Verilog EDUCATIONAL BACKGROUND: Qualification College/ School Board Year(s) Percentage/ CGPA B.E(ECE) Bapuji Institute of ... - 2021 Feb 14

Data Design

Vasant Nagar, Karnataka, India
... VLSI Domain Skills Operating systems: Linux, Windows HDLs : Verilog HVLs : System Verilog Verification Methodologies : UVM EDA tools: Aldec, Model Sim, ISE. Domain: Digital Design,ASIC/FPGA design flow, Methodologies. Knowledge on: RTL Coding, FSM ... - 2021 Feb 13

Engineer Engineering

Vasant Nagar, Karnataka, India
... • Hardware Description Language: Verilog, system Verilog. • Architectures: Micro processor 8085,Microcontroller 8086. • Matematical tools: MATLAB. • Hardware expertise: Altera FPGA board, Feko+ winprop 2018 software. Workshops attended/Papers ... - 2021 Feb 13

Design Data

Bangalore, Karnataka, India
... Education(CBSE) 2013 9.8(CGPA) TECHNICAL SKILLS: Programming Languages : 1) Verilog 2) C 3) C++ (Basic) Software Exposure : 1) Cadence 2) Xilink ISE 3) ModelSim 4) ngSPICE 5) MAGIC 6) CodeBlocks TRAINING & COURSES: Knowledge on System Verilog. ... - 2021 Feb 12

Design Engineer Digital

Bangalore, Karnataka, India
... • TOOLS: IC Compiler, Primetime, Verilog programming in Xilinx. • CONCEPTS: Physical Design, STA, CTS, Digital electronics, . • DESIGNING: Digital Modules, State machines, Physical Design (PnR) project in IC Compiler. COMPETENCIES : • Finished a ... - 2021 Feb 12

Design Engineering

Vasant Nagar, Karnataka, India
... Technical skills: VLSI Domain skills: HDL: Verilog HVL: System Verilog Verification methodology: Coverage driven verification, Assertion based verification TB Methodology: UVM EDA Tools: Questa-Sim – Mentor Graphics Riviera Pro – Aldec ISE - Xilinx ... - 2021 Feb 12

Design Engineering

Vasant Nagar, Karnataka, India
... • Good hands-on experience in System Verilog,Verilog . • Good hands on Experience in implementing Constraint based Randomised testbenches for Design blocks using EDA tool. • Hands-on experience in UVM . • Exposure with databases using SQL. • ... - 2021 Feb 12

Engineering Security

Vasant Nagar, Karnataka, India
... U 7.7 2019 PUC SDM pre university college, Ujire Department of Pre-University Education 84.5 2015 SSLC National high school konandur Karnatka Secondary Education Examination Board 92.32 2013 IT PROFICIENCY Languages C, assembly (embedded), Verilog. ... - 2021 Feb 12

Design Project

Vasant Nagar, Karnataka, India
... Software: C, C++, Verilog, VHDL, Physical layout, Analog layout, Memory layout Standard Cell layout design, ASIC, LVS, DRC, Embedded C. 2. Software Tools: MATLAB Simulink, Xilinx ISE, Cadence Virtuoso, GLADE, Mentor Graphics, Spice simulation. 3. ... - 2021 Feb 12
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