MOUNIKA JUJJUVARAPU

*st

cross road, Gmail ID : adj2bl@r.postjobfree.com.

Opposite to Kalamandir, Phone No : +917*********.

Aswath nagar, LinkedinId : https://www.linkedin.com/ Marathahalli,

Bengaluru,Karnataka-560037.

in/mounika-jujjuvarapu-41444b188

Objective

Seeking a challenging environment that encourages continuous learning and creativity,providing exposure to new ideas that stimulates professional and personal growth Skill Set

Programming Language : Verilog HDL, System Verilog Verification methodology : UVM

Tools : ALDEC Riviera Pro

Software skills : Basic of C

Platforms : Windows, Linux

Scripting : Perl, Tcl

Protocols : AMBA-APB, AMBA-AHB Lite

Training Experience

• Being trained as Design and Verification engineer at QsoCs Technologies for 6 months. Academic Profile

Qualification University/Board

Year of

passing

Aggregate B. Tech

(Electronics and

Communication

Engineering)

SPMVV,

TIRUPAT HI

2019

71

Intermediate

(MPC)

Board of

Intermediate

Education

2015

93

SSC Secondary Board

of Education

2013 93

PROJECTS

Project-1:

Title : Verification of AMBA-Advanced High Performance Bus(AHB) protocol.

Language : System Verilog.

Methodology : UVM.

Description : AMBA AHB-Lite addresses the requirements of high performance synthesizable designs. It is a bus interface that supports a single bus master and provides high -bandwidth operation.

Responsibilities:

• Prepared Verification plan based on design specification.

• Developed various components in UVM Testbench Architecture.

• Developed slave verification environment to verify the AHB master. Project-2:

Title : Verification of AMBA-Advanced Peripheral Bus (APB) protocol. Language : System Verilog.

Methodology : UVM.

Description : AMBA APB addresses the requirements of low performance synthesizable designs. It is a bus interface that supports a single bus master and multiple slaves and provides low-bandwidth operation. Responsibilities:

• Prepared design verification plan based on design specification.

• Verified AMBA APB slave RTL in System Verilog and UVM. Project-3:

Title : Design and verification of Asynchronous FIFO. Language : Verilog and System Verilog.

Description : A memory in which the data word that is written in first comes out first is a first-in first-out memory.

Responsibilities:

• Developed internal blocks of Asynchronous FIFO design in Verilog.

• Prepared Verification plan based on design specification.

• Developed various components in SV Testbench Architecture and verified with the same. Declaration

I hereby declare that the information above furnished is true to the best of my knowledge. Place: Regards

Date: (MOUNIKA JUJJUVARAPU)

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