| Resume alert | Resumes 11 - 20 of 23 |
Project Data Analysis
Ahmedabad, GJ, India
... PROJECTS ASIC Projects : 1.)Vital Sign Analysis in ASIC Domain: Duration: July 2013-June 2014 Team Size: 1 HDL/HVL: Verilog, System Verilog EDA Tool: Xilinx, Questa Sim, Synopsys DC Compiler, LabVIEW I have implemented layered test bench environment ... - 2016 Jan 27
... PROJECTS ASIC Projects : 1.)Vital Sign Analysis in ASIC Domain: Duration: July 2013-June 2014 Team Size: 1 HDL/HVL: Verilog, System Verilog EDA Tool: Xilinx, Questa Sim, Synopsys DC Compiler, LabVIEW I have implemented layered test bench environment ... - 2016 Jan 27
Design Higher Secondary
Ahmedabad, GJ, India
... ModelSim, HDL Companion, Xilinx ISE 12.0, Xilinx Vivado, Altium (PCB) Operating Systems Linux and Windows VLSI SKILLS: HDL : Verilog and VHDL HVL : System Verilog Bus Protocol : AMBA AXI Lite and AHB Serial Protocol : UART, I2C, SPI Knowledge : RTL ... - 2015 Oct 18
... ModelSim, HDL Companion, Xilinx ISE 12.0, Xilinx Vivado, Altium (PCB) Operating Systems Linux and Windows VLSI SKILLS: HDL : Verilog and VHDL HVL : System Verilog Bus Protocol : AMBA AXI Lite and AHB Serial Protocol : UART, I2C, SPI Knowledge : RTL ... - 2015 Oct 18
Engineering Testing
Ahmedabad, GJ, India
... VERILOG Packages: Xilinx ISE, Kiel (8051Controller), Eagle (PCB Design) PROJECT Title: Prepaid Electricity Meter Description: The proposed system uses the services of telecom operators for meter reading and mobile banking or net banking for billing. ... - 2015 Sep 06
... VERILOG Packages: Xilinx ISE, Kiel (8051Controller), Eagle (PCB Design) PROJECT Title: Prepaid Electricity Meter Description: The proposed system uses the services of telecom operators for meter reading and mobile banking or net banking for billing. ... - 2015 Sep 06
Engineer High School
Ahmedabad, GJ, India
... ST.XAVIER\'s High School,Loyola Hall Ahmedabad, Gujarat 12th Science, Grade: 80.60 2004 - 2005 Shree Vidyanagar Secondary & Higher Secondary School Ahmedabad, Gujarat 10th, Grade: 90.70 2002 - 2003 SKILLS • Languages: Perl, Tcl/Tk, Verilog, Assembly ... - 2015 Jan 09
... ST.XAVIER\'s High School,Loyola Hall Ahmedabad, Gujarat 12th Science, Grade: 80.60 2004 - 2005 Shree Vidyanagar Secondary & Higher Secondary School Ahmedabad, Gujarat 10th, Grade: 90.70 2002 - 2003 SKILLS • Languages: Perl, Tcl/Tk, Verilog, Assembly ... - 2015 Jan 09
Engineering Engineer
Ahmedabad, GJ, India
... Used Synopsys tool chain to perform this project from RTL to GDS-II form Design and synthesize the cache controller Designed cache controller Verilog RTL for 1KB fully associative write back buffer cache. Used Synopsys tool chain for simulation, ... - 2014 Nov 03
... Used Synopsys tool chain to perform this project from RTL to GDS-II form Design and synthesize the cache controller Designed cache controller Verilog RTL for 1KB fully associative write back buffer cache. Used Synopsys tool chain for simulation, ... - 2014 Nov 03
Electronics design Engineer
Ahmedabad, GJ, India
... TOOLS AND LANGUAGE SKILLS Programming languages: C and C++ (basic) HDL: VHDL and VERILOG (basic coding) Cadence tools: Virtuoso Layout Editor, Schematic Composer, Spectre Environment, DRC, LVS Board Design Tool: ModelSim (Altera) VHDL Simulation: ... - 2014 Oct 13
... TOOLS AND LANGUAGE SKILLS Programming languages: C and C++ (basic) HDL: VHDL and VERILOG (basic coding) Cadence tools: Virtuoso Layout Editor, Schematic Composer, Spectre Environment, DRC, LVS Board Design Tool: ModelSim (Altera) VHDL Simulation: ... - 2014 Oct 13
Engineer Design
Gandhinagar, GJ, India
... • Expertise in writing Verilog/Systemverilog designs from specifications, Static Timing Analysis, Verification using Systemverilog Testbenches including Directed and Random testcases generation, Perl scripting. • Solid background in Digital Logic ... - 2014 Oct 01
... • Expertise in writing Verilog/Systemverilog designs from specifications, Static Timing Analysis, Verification using Systemverilog Testbenches including Directed and Random testcases generation, Perl scripting. • Solid background in Digital Logic ... - 2014 Oct 01
Design Training
Ahmedabad, GJ, 380015, India
... CBSEin 2008 with 74.6% Class X fromRajkamalSaraswatiVidyaMandir, Dhanbad under CBSE in 2006 with 73.4% TECHNICAL SKILLS: Programming languages : C, C++,VHDL, Verilog Simulation Software :Proteus7professional, Pspice, Xilinx,Tanner PROJECTS: B. ... - 2014 Jul 29
... CBSEin 2008 with 74.6% Class X fromRajkamalSaraswatiVidyaMandir, Dhanbad under CBSE in 2006 with 73.4% TECHNICAL SKILLS: Programming languages : C, C++,VHDL, Verilog Simulation Software :Proteus7professional, Pspice, Xilinx,Tanner PROJECTS: B. ... - 2014 Jul 29
Training College
Ahmedabad, GJ, 380015, India
... Professional Training :- • Pursued 6 weeks Training in CMC LIMITED GREATER NOIDA in which I have learned about Verilog and worked on the software of MODELSIM. Personal Details :- Father’s Name : Mr. Jay Krishna Maheshwari Mother’s Name : Mrs. Tanuja ... - 2014 Jul 28
... Professional Training :- • Pursued 6 weeks Training in CMC LIMITED GREATER NOIDA in which I have learned about Verilog and worked on the software of MODELSIM. Personal Details :- Father’s Name : Mr. Jay Krishna Maheshwari Mother’s Name : Mrs. Tanuja ... - 2014 Jul 28
Training Visual Basic
Ahmedabad, GJ, India
... Programming Skills Assembly language for 8051 and 8085, C,Python(Basic), VHDL(medium),verilog(medium), Visual Basic(Basic). Operating Systems Windows 7,XP,LINUX,RASPBERRY PI,XBMC. ACADAMIC DETAILS Examination Board/University Month/Year % Marks/C.P ... - 2014 Jun 10
... Programming Skills Assembly language for 8051 and 8085, C,Python(Basic), VHDL(medium),verilog(medium), Visual Basic(Basic). Operating Systems Windows 7,XP,LINUX,RASPBERRY PI,XBMC. ACADAMIC DETAILS Examination Board/University Month/Year % Marks/C.P ... - 2014 Jun 10