| Resume alert | Resumes 11 - 20 of 21 |
Engineering Safety
Allahabad, Uttar Pradesh, India
... Ram Badan chauhan Date of Birth :03-07-1993 Maritalstatus :Single Gender :Male Languages Known :English,Hindi Hobby : Playing Cricket,playing game on pc DECLARATION:- I do here by declare that the particulars of information and facts stated here in ... - 2019 Sep 10
... Ram Badan chauhan Date of Birth :03-07-1993 Maritalstatus :Single Gender :Male Languages Known :English,Hindi Hobby : Playing Cricket,playing game on pc DECLARATION:- I do here by declare that the particulars of information and facts stated here in ... - 2019 Sep 10
C English
Allahabad, Uttar Pradesh, India
... COURSES NO DATE OF ISSUE PLACE OF ISSUE PRE-SEA RATING CMETL/GPR/001/034 21.06.2014 LUCKNOW SSDS CMETL/STSDSD/131/1840 07.06.2014 LUCKNOW PST RAM/RPST/5098 12.11.2016 MUMBAI FPFF RAM/RFPFF/5101 23.11.2016 MUMBAI PSSR RAM/PSSR/15410 08.12.2016 MUMBAI ... - 2019 May 07
... COURSES NO DATE OF ISSUE PLACE OF ISSUE PRE-SEA RATING CMETL/GPR/001/034 21.06.2014 LUCKNOW SSDS CMETL/STSDSD/131/1840 07.06.2014 LUCKNOW PST RAM/RPST/5098 12.11.2016 MUMBAI FPFF RAM/RFPFF/5101 23.11.2016 MUMBAI PSSR RAM/PSSR/15410 08.12.2016 MUMBAI ... - 2019 May 07
Office High School
Prayag, Uttar Pradesh, India
... Ram Lal Date of birth : 14th Sep 1989 Language know : English & Hindi Marital status : Singal Gender : Male Nationality : Indian Permanent Address : Godhrauli, Post – Aung,Disst.- Fatehpur (U.P.) Declaration I here by declare that the information ... - 2018 Nov 19
... Ram Lal Date of birth : 14th Sep 1989 Language know : English & Hindi Marital status : Singal Gender : Male Nationality : Indian Permanent Address : Godhrauli, Post – Aung,Disst.- Fatehpur (U.P.) Declaration I here by declare that the information ... - 2018 Nov 19
Sales Representative Manager
Prayag, Uttar Pradesh, India
... CMPUTER KNOWLEDGE Ms office,Exel,ms words,online work,ERP work email and word pad etc Personal Details : Date of Birth : 30 June 1980 Father Name : Shri Ram Narayan Bhardwaj Marital Status : Married Language Known : English, Hindi Permanent Address ... - 2018 Sep 10
... CMPUTER KNOWLEDGE Ms office,Exel,ms words,online work,ERP work email and word pad etc Personal Details : Date of Birth : 30 June 1980 Father Name : Shri Ram Narayan Bhardwaj Marital Status : Married Language Known : English, Hindi Permanent Address ... - 2018 Sep 10
B.Tech in Mechanical Engineering
Allahabad, Uttar Pradesh, India
... PERSONAL DETAILS Father’s Name :- Mr.Ram Kripal Permanent Address :- Barha Kalan Baheliyapur Meja Allahabad U.P. Date of Birth :- 10 february 1994 Language Known :- English & Hindi Marital Status :- Single Nationality/Religion :- Indian / Hindu ... - 2018 Jul 18
... PERSONAL DETAILS Father’s Name :- Mr.Ram Kripal Permanent Address :- Barha Kalan Baheliyapur Meja Allahabad U.P. Date of Birth :- 10 february 1994 Language Known :- English & Hindi Marital Status :- Single Nationality/Religion :- Indian / Hindu ... - 2018 Jul 18
Power Plant Engineer
Allahabad, UP, India
RAM SAGAR SAROJ S/O HORI LAL INDIAN D.O.B : *th FEB 1990 M.NO : 075******** EMAIL.ID : ac3ezz@r.postjobfree.com Self motivated, skilled at rapidly integrating new knowledge, and a creative problem solver. I “Seeking a position in an office ... - 2017 Nov 20
RAM SAGAR SAROJ S/O HORI LAL INDIAN D.O.B : *th FEB 1990 M.NO : 075******** EMAIL.ID : ac3ezz@r.postjobfree.com Self motivated, skilled at rapidly integrating new knowledge, and a creative problem solver. I “Seeking a position in an office ... - 2017 Nov 20
Design Information Technology
Allahabad, UP, India
... HDL/HVL : System Verilog, UVM EDA Tools: Questasim > Real Time Clock, Dual Port RAM, APB- slave - RTL design and verification . HDL/HVL: Verilog, SystemVerilog . EDA Tools: Questasim . Implemented the RTL using Verilog HDL independently . ... - 2015 May 13
... HDL/HVL : System Verilog, UVM EDA Tools: Questasim > Real Time Clock, Dual Port RAM, APB- slave - RTL design and verification . HDL/HVL: Verilog, SystemVerilog . EDA Tools: Questasim . Implemented the RTL using Verilog HDL independently . ... - 2015 May 13
Design Engineering
Allahabad, UP, India
... Real Time Clock, Dual Port RAM, APB- slave - RTL design and verification HDL: Verilog HVL: SystemVerilog EDA Tools: Incisive Enterprise Simulator, RTL compiler and ISE > Implemented the Real Time Clock using Verilog HDL independently > Architected ... - 2015 Jan 29
... Real Time Clock, Dual Port RAM, APB- slave - RTL design and verification HDL: Verilog HVL: SystemVerilog EDA Tools: Incisive Enterprise Simulator, RTL compiler and ISE > Implemented the Real Time Clock using Verilog HDL independently > Architected ... - 2015 Jan 29
Engineer High School
Allahabad, UP, India
... Ram Dularey : 24th Oct 1992 Date of Birth Gender : Male Marital status : Married Nationality : Indian Language know : English & Hindi Date Place (RAJESH KUMAR) - 2013 Oct 05
... Ram Dularey : 24th Oct 1992 Date of Birth Gender : Male Marital status : Married Nationality : Indian Language know : English & Hindi Date Place (RAJESH KUMAR) - 2013 Oct 05
Technology University
Allahabad, UP, India
... Worked as Expert in the section of Agriculture Extension (Horticulture) in Bioved Research Institute of Agriculture & Technology Ram Van Gaman Road (Bhagotipur Chauraha) Singverpur, Allahabad from 10 June 2009 to 16 August 2010. 6. Delivering ... - 2013 Apr 17
... Worked as Expert in the section of Agriculture Extension (Horticulture) in Bioved Research Institute of Agriculture & Technology Ram Van Gaman Road (Bhagotipur Chauraha) Singverpur, Allahabad from 10 June 2009 to 16 August 2010. 6. Delivering ... - 2013 Apr 17