Design Engineering

Ketan Jadav

Email: **********@*****.**.**

M.tech-(Microelectronics) 2nd year.

*********@*****.*** IIIT-Allahabad,

Linkedin id: https://www.linkedin.com/in/ketanjadav

Deoghat,Jhalwa,U.P.(INDIA)

Mobile: +91-979*******,+91-982**-*****.

Summary of Qualifications

> Good understanding of the ASIC and FPGA design flow

> Experience in writing RTL models in Verilog HDL and test benches in

SystemVerilog

> Very good knowledge in verification methodologies

> Experience in using industry standard EDA tools for the front-end

design, back-end design and verification

VLSI Domain Skills

HDLs : Verilog and VHDL

HVL : SystemVerilog and PSL

Software language : C, C++, OOP

Verification Methodologies : Coverage Driven Verification

Assertion Based Verification

TB Methodology : UVM

EDA Tool : synopsys: VCS, DesignCompiler,

ICC, Prime time

Cadence: Encounter, Virtuoso, Assura, Nc-sim

Mentor Graphics: Questasim, Precision, Modelsim

Xilinx: ISE, XST, Isim

Domain : ASIC/FPGA Design Flow,

Digital Design methodologies

Knowledge : RTL Coding, FSM based

design, Simulation,

Code

Coverage, Functional Coverage, Synthesis,

Static

Timing Analysis, DFT, ABV, FPGA Prototyping.

Achievement:

> Winner of 5th Annual All India Mentor Graphics University Design

contest-2014.

Professional Qualification

> Pursuing M.tech (Microelectronics) at Indian Institute of Information

Technology, Allahabad (Current CGPA=8.25 aggr.)

> Accel certified VLSI DESIGN course from Accel IT Academy(Now Known as

Maven Silicon), Bangalore

Year: Aug. 2009

> Bachelor of Engineering, Govt. Engineering College, Modasa.

Hemchandracharya North Gujarat University, India

Discipline: Electronics & communication engineering

Percentage: 61.66% First Class

Year:

May 2008

Thesis Topic:

> ASIC Implementation of AES for CMOS 28nm technology (with High

Throughput).

Experience

> Aug. 2009 - Dec. 2009, training, Accel IT Academy (MAVEN SILICON).

> From Aug-2010 to June-2013 worked as lecturer at Ahmedabad institute

of technology during this tenure I supervised VLSI project like ADC,

DAC, PS2 interface, DES, Embedded project.

> From July-2013 pursuing M.tech (Microelectronics) at IIIT-Allahabad.

VLSI Projects

Two car vertical elevator-RTL design and verification

HDL: system verilog

HVL: system verilog

EDA Tools: Questasim 10.3c.

> Design algorithm for 2-car vertical elevator.

> Design and verify RTL design using system verilog.

Real Time Clock, Dual Port RAM, APB- slave - RTL design and

verification

HDL: Verilog

HVL: SystemVerilog

EDA Tools: Incisive Enterprise Simulator, RTL compiler and ISE

> Implemented the Real Time Clock using Verilog HDL independently

> Architected the class based verification environment using

SystemVerilog

> Verified the RTL model using SystemVerilog.

> Generated functional and code coverage for the RTL verification sign-

off

> Synthesized the design

Video Graphics Adaptor, VLIW, AES, UART, DES, ADC-DAC CONTROLLER - RTL

Design and Verification

HDL: Verilog

EDA Tools:

Incisive Enterprise Simulator, RTL compiler and ISE

Architected the design

> Implemented the RTL using Verilog HDL

> Verified the RTL using Verilog HDL

> Implemented the design on the Spartan, Xilinx FPGA and verified the

design on the board

Engineering College Project

> 1st Sem of M.tech project on VGA controller with higher resolution and

generate different shape with motion using Xilinx Spartan3 Board.

> 8th semester (B.tech) 6 month training at Modsonic Instrument Pvt.

Ltd., Ahmadabad (Gujarat).

Project Details (B.tech Final Year)

(4*4)Keyboard Multi-Purpose & Rotary Encoder

HDL: VHDL

EDA TOOLS: XILLINX, MODELSIM

Architected the design

> Implemented the RTL using Verilog HDL

> Verified the RTL using Verilog HDL

> Implemented the design on the Spartan, Xilinx FPGA and verified the

design on the board

Other Engineering Project (3rd & 5th Sem.)

> Digital temperature indicator which shows temperature on LCD.

> Variable D.C. Power Supply (0v-30v).

Extra Curriculum Activities

> Attended the complementary seminar on MATLAB & Simulink for

engineering education, year-2012.

> Participated in one day "Tutorial on 8051 Microcontroller and its

laboratory Experiments" at EC department of Alpha college of

Engineering and Technology, year-2011.

> Attend 1 day workshop on synopsys vlsi design tool by Eigen

Technologies at IIIT-Allahabad.

> Attend 1 day workshop on cadence vlsi design tool by Entuple

Technologies at IIIT-Allahabad.

DECLARATION

I hereby declare that all the details furnished above are true to the

best of my knowledge.

Place : Allahabad (U.P.)

Ketan Jadav

Date :

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