KETAN JADAV

M.tech-(Microelectronics),

INDIAN INSTITUTE OF INFORMATION TECHNOLOGY,Allahabad

https://www.linkedin.com/in/ketanjadav

Email ID:acpnm4@r.postjobfree.com

Mobile No.097********

SUMMARY OF QUALIFICATIONS

. Good understanding of the ASIC and FPGA design flow.

. Experience in writing RTL models in Verilog HDL and test benches in

SystemVerilog.

. Very good knowledge in Analog and Digital Design Flow.

. Sound knowledge in Digital Electronics and synthesizable hardware design.

VLSI DOMAIN SKILLS

HDLs Verilog and VHDL

HVL

SystemVerilog and PSL

Verification Methodologies UVM

EDA Tool Synopsys:

VCS, DesignCompiler, ICC, Prime time

Cadence: Encounter, Nc-sim,Virtuoso,Assura

Mentor Graphics: Questasim, Precision,

Modelsim

Xilinx: ISE, XST, Isim

Knowledge STA,DRC,LVS,Verification

methodology,MATLAB,RTL

design,RC Extration,CTS,functional coverage,

Assertion base verification,C,OOP,

script(TCL,PERL)

WINNER OF 5TH ANNUAL ALL INDIA MENTOR GRAPHICS DESIGN CONTEST-2014.

It's all India Design contest for colleges and Universities. 100+ teams

are participated in this contest.

Problem Definition: Design RTL and Verification code for 2-Car vertical

Elevator system.

Language Used: System Verilog and UVM (Methodology).

EDUCATIONAL QUALIFICATION

Degree/Examinatio Institution Year Performance

n

M.Tech IIIT Allahabad 2013-15 8.75/10

Microelectronics (UP)

B.E. (ECE) Government 2004-2008 65.66%

Engineering

College,Modasa,

Gujarat

Class-XII Saurabh High 2004 58.77(All sub)

(G.H.S.E.B.) School. 70.16(PCMB)

Class-X(G.S.E.B.) Navjyot 2002 81.86

Vidhyalay

TRAINING AND WORK EXPERIENCE

. Accel certified VLSI Verification course from Accel IT Academy(Now

Known as Maven Silicon),Bengluru.

. Aug-2010 to June-2013 worked as lecturer at Ahmedabad institute of

technology.

PROJECT

M.Tech Thesis

> Design Advance Encryption Standard with High throughput

Design and Implementation of High throughput Advance Encryption

Standard on FPGA and It's ASIC Design using synopsys 32nm

technology. I have approached pipelining concept with BRAM and

Without BRAM to increase throughput.Design verify on FPGA Board using

UART with various scenario. ASIC design verified by VCC simulatior

after placement and routing which gives satisfactory results without

timing vilolation.Both FPGA and ASIC desing shows improvement in

throughput.

HDL:verilog

EDA Tools:Xilinx ISE,Questasim,precision,Design compiler,ICC,VCS

Other Project

> Two car vertical elevator-RTL design and verification

Design a RTL and Verification Code for 2-car vertical elevator with

20 floors, each car can move up-down independently on same shaft (one

top of above). The Sum of Average Waiting Time (AWT) and Average

Dropping Time (ADT) is as minimum as possible irrespective

of avoid collision. Test-bench can use constraint-random,

coverage and assertion based methodology of System Verilog.

HDL/HVL : System Verilog, UVM

EDA Tools: Questasim

> Real Time Clock, Dual Port RAM, APB- slave - RTL design and

verification

. HDL/HVL: Verilog, SystemVerilog

. EDA Tools: Questasim

. Implemented the RTL using Verilog HDL independently

. Architected the class based verification environment using SystemVerilog

. Verified the RTL model using SystemVerilog

. Generated functional and code coverage for the RTL verification sign-off

. Synthesized the design

> Video Graphics Adaptor, VLIW, UART, DES, ADC-DAC CONTROLLER,Rotary

Counter with 4x4 customize multifunction keypad - RTL Design and

Verification

. HDL: Verilog

. EDA Tools: Questasim,ISE

. Architected the design

. Implemented the RTL using Verilog HDL

. Verified the RTL using Verilog HDL

. Implemented the design on the Spartan series-Xilinx FPGA and verified the

design on the development board

DECLARATION

I hereby declare that all the details furnished above are true to the

best of my knowledge.

Date : 07-05-2015

Place : Allahabad(U.P.)

Ketan Jadav

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