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Driver Data
Jaipur, Rajasthan, India
... ground structure -> Use HFSS software to design and optimize the performance of antenna parameters using different shapes on ground -> Implement the same concept in Matlb and made GUI Low Power FIR Filter using Xilinx FPGA Area: VLSI Guide: Dr. ... - 2019 May 05
... ground structure -> Use HFSS software to design and optimize the performance of antenna parameters using different shapes on ground -> Implement the same concept in Matlb and made GUI Low Power FIR Filter using Xilinx FPGA Area: VLSI Guide: Dr. ... - 2019 May 05
Engineer System
Jaipur, RJ, 302001, India
... Field of Interest: RTL Design, Verilog, FPGA, SystemVerilog, UVM, Linux, Automation and Embedded System. OORRCCAADD PP ssppiiccee ddeessiiggnn aanndd ssiimmuullaattiioonn CCMMOOSS VVLLSSII DDeessiiggnn VVeerriilloogg aanndd SSyysstteemm ... - 2016 Aug 17
... Field of Interest: RTL Design, Verilog, FPGA, SystemVerilog, UVM, Linux, Automation and Embedded System. OORRCCAADD PP ssppiiccee ddeessiiggnn aanndd ssiimmuullaattiioonn CCMMOOSS VVLLSSII DDeessiiggnn VVeerriilloogg aanndd SSyysstteemm ... - 2016 Aug 17
Project School
Jaipur, RJ, 302001, India
... School RBSC 63.44 2008 Technical Skill: Software : Keil(embedded c or assembly language) Mp lab Avr Studio 6 Proteus ISIS Xilinx 14.7 (VHDL) Arduino Hardware : PCB Designing or Bread board FPGA AT89C52 At mega8/16/32 Indusial Training: CDAC Moahli ... - 2016 Feb 09
... School RBSC 63.44 2008 Technical Skill: Software : Keil(embedded c or assembly language) Mp lab Avr Studio 6 Proteus ISIS Xilinx 14.7 (VHDL) Arduino Hardware : PCB Designing or Bread board FPGA AT89C52 At mega8/16/32 Indusial Training: CDAC Moahli ... - 2016 Feb 09