C,Java,Python

Bhargavi. V

Mobile: +91-917*******

Email Id : ********************@*****.***

Objective

To secure a challenging position and recognition on workplace, where I can effectively contribute my skills for the growth of the organization through hard work.

Educational Qualification

Year

Course

Institute

Percentage

2018

B.Tech (ECE)

MLR Institute of Technology

73

2014

Intermediate

Narayana Junior College

97

2012

SSC

Triveni Talent High school

8.8(GPA)

Technical Proficiency:

Languages : C, Python, Java,Verilog.

Scripts : TCL, Perl.

Packages : MS Office.

OS : UNIX

Project Details

Project1:

Title: Audio signal processing

Tools: Incisive, Genus, Tempus, Innovus, Vivado, Matlab - Simulink

Description: As per the requirements, Implemented the design both on FPGA and PD. Designing a controller which acts as a interface for processing the input audio signals into segregated noiseless audio output.

Target FPGA board used : Zync FPGA board

Physical Design : INNOVUS

Role:

•Based on the specifications, done the Block level Implementation, RTL simulation and Synthesis using Incisive.

•The analysis of pre and post-layout timing has been done using Tempus.

•Using Innovus completed the physical design by reducing the DRV, timing violations and geometry violations at physical verification stage for the design.

•For FPGA Implementation, performed synthesis using Vivado.

•VIO generation for monitoring and driving the internal FPGA signals in real time.

•Performed Hardware co-simulation in Simulink for design verification.

Project 2:

Title: ASIC Entity

Tools: Tempus, Innovus.

Description: Performing Physical design flow with 29 macro and 18K gate count in 45nm technology with 250MHZ frequency. Performed complete Pnr flow avoiding congestion and fixing timing violations.

Role:

•Pre-layout Static Timing Analysis in Tempus.

•Understanding of PVT, OCV, CPPR, and their effects on timing.

•Faced few problems during power planning because of the high macro count.

•After Power Planning cleared the design with no unconnected pins & dangling wires.

•After Placing the Standard cells checking setup timing analysis, DRC & Congestion.

•Fixing Hold violations after CTS.

•Physical Verification (Understanding and resolving of LVS, DRC, Antenna Violations).

Personal Details

Name : Bhargavi. V

Gender : Female

Address : 102, Lakshmi’s meridian, Lingampally, Hyderabad

Pin Code : 500019.

Declaration

I hereby declare that the information furnished above is true to the best of my knowledge.

Place: Hyderabad (Bhargavi. V)

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