| Resume alert | Resumes 91 - 100 of 124 |
Management Electrical Engineer
Chennai, TN, India
... design Project 1: CDMA Scheduler Implementation Tools : Xilinx, Cadence Language : Verilog Description: The generated Bus Arbiter consists of a D flip flop, priority logic blocks, an M bit ring counter and an M input OR Gates as shown in figure. ... - 2016 Nov 25
... design Project 1: CDMA Scheduler Implementation Tools : Xilinx, Cadence Language : Verilog Description: The generated Bus Arbiter consists of a D flip flop, priority logic blocks, an M bit ring counter and an M input OR Gates as shown in figure. ... - 2016 Nov 25
Technical Power
Chennai, TN, India
... ULTRA-LOW POWER SRAM DESIGN USING 9nm TFET: Design of a ultra-low power 8T Tunnel FET SRAM cell and Verilog-A model is used as instances in cadence virtuoso.To realized different SRAM designs of 6T Inwards, 6T Outwards and 8T.The proposed 8T SRAM ... - 2016 Jun 27
... ULTRA-LOW POWER SRAM DESIGN USING 9nm TFET: Design of a ultra-low power 8T Tunnel FET SRAM cell and Verilog-A model is used as instances in cadence virtuoso.To realized different SRAM designs of 6T Inwards, 6T Outwards and 8T.The proposed 8T SRAM ... - 2016 Jun 27
Engineering Secondary School
Chennai, TN, India
... Attended a workshop on “BASIC ELECTRONICS & PCB DESIGN USING CADENCE ORCAD/ALLEGRO 16.5” organized by PINE ROBOTECH,in Jeppiaar engineering college on 21th & 22nd August 2014. Attended a INTERNATIONAL WORKSHOP on ANDROID APPLICATION DEVELOPMENT ... - 2016 Jun 25
... Attended a workshop on “BASIC ELECTRONICS & PCB DESIGN USING CADENCE ORCAD/ALLEGRO 16.5” organized by PINE ROBOTECH,in Jeppiaar engineering college on 21th & 22nd August 2014. Attended a INTERNATIONAL WORKSHOP on ANDROID APPLICATION DEVELOPMENT ... - 2016 Jun 25
vhdl,verilog,c,embedded c
Chennai, TN, India
... 4) Workshops Attended Participated in workshop on Low power design and verification using cadence. Participated in the workshop on “Image processing framework using FPGA”. 5)Implant Training Three days in A-Bond Strands Private Limited, Chennai ... - 2016 Jun 21
... 4) Workshops Attended Participated in workshop on Low power design and verification using cadence. Participated in the workshop on “Image processing framework using FPGA”. 5)Implant Training Three days in A-Bond Strands Private Limited, Chennai ... - 2016 Jun 21
Secondary School Microsoft Office
Chennai, TN, India
... Matriculation Higher Secondary School Matriculation 2010 81.2 Area of Interest: Electronic Devices And Circuit Cadence tool VLSI Project: Design and simulation of area and delay efficient VLSI architecture by AES algorithm using CADENCE TOOL. ... - 2016 Jun 13
... Matriculation Higher Secondary School Matriculation 2010 81.2 Area of Interest: Electronic Devices And Circuit Cadence tool VLSI Project: Design and simulation of area and delay efficient VLSI architecture by AES algorithm using CADENCE TOOL. ... - 2016 Jun 13
Engineering Industrial Training
Chennai, TN, India
... AUTOCAD 3D MODELLING CADD CENTER INTERMEDIATE INDUSTRIAL TRAINING: Name of the Industry Training Area Duration of Training QMAX SYSTEMS INDIA PVT LTD., Poonamalle, Chennai PCB Design [Cadence], 6 MONTHS PERSONAL DETAILS Father’s Name : VEERARAJAN M. ... - 2016 May 25
... AUTOCAD 3D MODELLING CADD CENTER INTERMEDIATE INDUSTRIAL TRAINING: Name of the Industry Training Area Duration of Training QMAX SYSTEMS INDIA PVT LTD., Poonamalle, Chennai PCB Design [Cadence], 6 MONTHS PERSONAL DETAILS Father’s Name : VEERARAJAN M. ... - 2016 May 25
c,c++,matlab
Chennai, TN, India
... TECHNICAL SKILLS C, C++, MATLAB AREA OF INTEREST Embedded System Networking CO-CURRICULAR ACTIVITIES Attended workshop on “CADENCE Or CAD” Conducted by Jerusalem College of Engineering Undergone implant training UNIQ TECHNOLOGIES Industrial visit in ... - 2016 May 23
... TECHNICAL SKILLS C, C++, MATLAB AREA OF INTEREST Embedded System Networking CO-CURRICULAR ACTIVITIES Attended workshop on “CADENCE Or CAD” Conducted by Jerusalem College of Engineering Undergone implant training UNIQ TECHNOLOGIES Industrial visit in ... - 2016 May 23
Engineering Engineer
Chennai, TN, India
... TECHNICAL SKILLS: Programming languages :C, VISUAL BASIC 6.0 Designing Tools :KEIL, MATLAB, CADENCE, MULTISIM Assembly language :Microcontroller 8051, Microprocessor 8086 PLC (Programmable Logic Controllers), SCADA (Wincc & Wonderware), HMI (Human ... - 2016 May 06
... TECHNICAL SKILLS: Programming languages :C, VISUAL BASIC 6.0 Designing Tools :KEIL, MATLAB, CADENCE, MULTISIM Assembly language :Microcontroller 8051, Microprocessor 8086 PLC (Programmable Logic Controllers), SCADA (Wincc & Wonderware), HMI (Human ... - 2016 May 06
Engineering Software Developer
Chennai, TN, India
... Worked with clients named Fullerton india credit company ltd, Prizm, Amada, Unilever, Cadence. CERTIFICATIONS: Globally certified in SAP ABAP from ITBMS, the authorised SAP institute, Chennai with 71% in June 2015. CERTIFICATE ID : 001******* ... - 2016 Apr 15
... Worked with clients named Fullerton india credit company ltd, Prizm, Amada, Unilever, Cadence. CERTIFICATIONS: Globally certified in SAP ABAP from ITBMS, the authorised SAP institute, Chennai with 71% in June 2015. CERTIFICATE ID : 001******* ... - 2016 Apr 15
Design Engineering
Chennai, TN, India
... TECHNICAL SKILLS: Languages known: Basics of C and C++, VHDL, Verilog, System Verilog EDA Tools: Cadence Tools, Xilinx ISE, Vivado Design Suite Operating systems: Windows, Linux SKILL SET: Xilinx Tool Flow (Xilinx ISE and Vivado Design Suite) ... - 2016 Mar 12
... TECHNICAL SKILLS: Languages known: Basics of C and C++, VHDL, Verilog, System Verilog EDA Tools: Cadence Tools, Xilinx ISE, Vivado Design Suite Operating systems: Windows, Linux SKILL SET: Xilinx Tool Flow (Xilinx ISE and Vivado Design Suite) ... - 2016 Mar 12