V.P.Sampath

acxnbn@r.postjobfree.com

Cell: +919*********

Summary:

FPGA and ASIC RTL design for Communication Systems

Simulation, Design Synthesis, Implementation, PAR, Timing Simulation

Experience in FPGA prototyping of multi-million gate ASICs using Xilinx-Virtex-7,,Zed, Spartan6, Spartan3

Understanding of Power Management ( voltage domain, power domains, clock domains )

Low power synthesis(UPF and CPF)

Understanding of AXI protocols

Exposure to Simulators (ncsim )

Verilog/RTL/Conformal Verification( LEC)

Exposure to shell, TCL.

Familiarity with the GNU tool chain and Linux

PCB design for multi-layer, complex boards (up to 6 layers).

Range of appropriate CAD tools for schematics and PCB design, circuit simulators and FPGA design and simulation tools.

Independently handle the execution and delivery of a medium to complex blocks RTL2GDS implementation

Developed specifications for specific FPGA designs and assisted in parsing the work between FPGA designers.

Designed, developed wireless communications FPGA code for existing client products.

Provided development support for wireless communications FPGA for new client products as needed.

Adhered to the guidelines for code development as practiced by the engineering team.

International Client Exposure

Professional Experience:

NIELIT Chennai March 2013-Till date

Ram Innovation Labs, Chennai Oct 2008 – Feb 2013

Telesoft Neutek, Mumbai June 2008-Oct 2008

Freelancer- Ilakshya Private Limited Jul 2007 - Jun 2008

Leela Scottish Private Limited Jun 2004 – Jul 2005

The Builders, Trivanthapuram May 2001- June 2004

NIELIT Chennai

Responsibilities:HDL coding, FPGA Synthesis, ASIC design

Project 1: CDMA Scheduler Implementation

Tools : Xilinx, Cadence

Language : Verilog

Description: The generated Bus Arbiter consists of a D flip flop, priority logic blocks, an M bit ring counter and an M input OR Gates as shown in figure. To implement a BA, we employ token concept from a token ring in a network. The output (4 bits) of the ring counter act as the enable signals to the priority logic blocks. Only, one enabled priority logic block can assert a grant signal. The ack signal to the bus arbiter is delayed by one arbitration cycle by a D flip flop. The delayed ack signal pulls a trigger to the ring counter which is rotated one bit. Thus, the token bit is rotated left each cycle and the token is initialized to the reset phase.

Responsibilities:

Synthesis

Responsible for the FPGA implementation.

Ram Innovation Labs

Responsibilities: HDL coding, FPGA Synthesis

Project 2: Development of Special Coding Techniques To Compress Video Data

Tools: Xilinx

Language: Verilog

Description: The FPGA Implementation logic is to compress the data is with the3-level, 2-d separable DWT by decorrelation which has 9 taps for LPF and 7 taps for HPF.At each level of de-composition, the LL sub-band from the previous level is decomposed using a 2-d DWT & thus is replaced with 4 new sub-bands. Each new sub-band is half the width & height of the parent LL sub-band. Each additional level of decomposition thus increases the no. of sub bands by 3 but the total no. of DWT coefficients used to represent the image data are unchanged. For a 3-level decomposition, 19 sub bands are generated. The sub-bands are arranged to form an array of the same dimensions as the original image.

Responsibilities:

Synthesis

Responsible for the FPGA implementation of BPE.

Prepared User Manual

Project 3: FPGA Based Intrusion Detection

Tools : Xilinx

Language : Verilog

Description: TheFPGA logic for the Intrusion Detection in which the first block of the TCP/IP data is fed into the input state machine, which splits incoming packets up into a header and a payload part. The design unit involving two 32- bit adders and one 16 -bit adder. The Memory gateway takes the payload data and writes it to the appropriate position in its 32 bit wide memory. The Xilinx FPGA is used in this work and one such block Select RAM can be configured as a memory with different data widths and depths. One instance of the generic block is sufficient to serve the whole FPGA.The connection-specific blocks need to be instantiated once per connection. Alternatively one instance can serve all connections by using different memories with multiplexers.

Responsibilities:

FPGA implementation of the block FPGA.

Prepared User Manual

Project 4: CDMA Transmitter

Tools: Xilinx

Language: Verilog

Description: This project is developed upon the basis of wideband code division multiple access (WCDMA) technology which is a widely accepted 3G interface based on direct sequence (DS) CDMA technology. The Verilog hardware description language (Veiling HDL) is used to develop the prototype for an uplink WCDMA system. System clock is applied to FIR and modulation block.

Responsibilities:

RTL design

Synthesis.

Responsible for the FPGA implementation of CDMA transmitter.

Prepared User Manual

Telesoft Neutek Pvt Ltd Team Member June2008 –Sept 2008

Responsibilities: Telesoft Neutek Pvt Ltd

Appointing people/ vendors for execution of sourced content for VAS.

Internal data and information management

Monitoring of MIS reports generated by the team, which inturn would be submitted to the senior management for review

Monitoring of competition analysis with respect to their content pool, and highlight the essential information to senior management

Liase with the legal teams for ensuring that the agreements are in compliance to the policies and norms

Service &Product Development department for new value added service requests, initiates new platform projects that increase the efficiency of the infrastructure, analyzes and shapes the requested business model, forms a project plan with engineering team, initiates and manages the project-web portal, mobile portal. Experience in SQL, International exposure. Experience in Manual testing, report generation.Experience in value added services and managed services.Understanding of the offshore business. Good communication skills & handling with the client independently.

International Client Exposure:

Worked as a client interface with Bakrie Telecom, Jakarta in Indonesia. Product marketing and Back office operations.

Tenure June 20 –September 17.Worked in the development of a VIVA, Social networking platform

Role:SQL insertion, monitoring,application management

The Builders

Electrical engineer 2001-04

Determine optimal technical & commercial configuration and selection of technology.

Preparation of functional specifications.

Evaluation of proposals and selection of most optimal cost effective option.

Form part of management team in awarding contracts.

Education:

Anna University, Chennai 2007

ME in Applied Electronics - 70.2%

Madurai Kamaraj University, Madurai 2001

BE in Electrical & Electronics - 65.5%

Co-curricular Activities:

Editorial letters in the leading newspapers and in the Hindu Opportunities

Contributions in the EFY magazine 2015 editions in month August, December (2015)and February (2016),July and October editions

Columns appeared in the IEEE Institute, September 2012.

INTERNATIONAL CONFERENCES:

Accepted:

FPGA Based System For Multi-Vehicle Bus Controller

V. P. Sampath, V. Kasivishwanathan 2014 International Conference on e-Learning, e-Business, Enterprise Information Systems, and e-Government, World Congress of Engineering

Smart and efficient onboard image compression using reconfigurable Hardware"has been accepted for the IEEE-International Conference on “Emerging Trends in Science, Engineering, Business and Disaster Management” - ICBDM 2014 on 28th February, 2014 at Noorul Islam University, Kanyakumari.

“Image Compression For Space Onboard Remote Sensing”17th International Conference on Image Processing, Computer Vision, & Pattern Recognition July 22-25, 2013, Las Vegas, USA.

‘A Generic Architecture for on chip CDMA based switch’ at Euro micron Conference at Germany. May 2007.

References: Available on request

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