ABILASH.B

Mobile no: +919*********,+917*********

E-mail id : actwqy@r.postjobfree.com

CAREER OBJECTIVE:

I intend to build a career in a leading organization with a hi-tech environment, committed and dedicated people, who will help me, live up to my full potential. EDUCATIONAL QUALIFICATION:

Examination

Discipline/

Specialization

School/college

Board/

University

Year of

Passing

Percentage

%

ME

VLSI DESIGN

Sri Shakthi Institute of

Engineering and

Technology, Coimbatore

Anna

university

2013-

2015

7.6(cgpa)

BE

ELECTRONICS

AND

COMMUNICATION

Tamilnadu College of

Engineering, Coimbatore

Anna

university

2009 –

2013

7.5(cgpa)

Higher

Secondary

BIOLOGY,MATHS,

PHYSICS,

CHEMISTRY

Adharsh Vidyalaya

Higher Secondary School,

Anthiyur

Tamilnadu

State Board

2007 –

2009 93%

S. S. L.C S.S.L.C

VSVMS,

Kotagiri

Matriculation

Board

2007 88%

WORK EXPERIENCE:

Intern at “Intel Technology India Pvt. Ltd., Bangalore” for 6 months ( july ’14 to february ’15) Description: On-board testing of data transfer protocols using FPGA, for wearable applications.

UART interfacing

SPI interfacing

I2C interfacing

Interfacing of Bluetooth and LCD module

Integration of third party hardware eg. Arduino to implement the serial data transfer protocols between the FPGA and the external board

FPGAs used: Xilinx zynq zc702, Xilinx virtex vc707. TECHNICAL SKILLS:

Languages known: Basics of C and C++, VHDL, Verilog, System Verilog EDA Tools: Cadence Tools, Xilinx ISE, Vivado Design Suite Operating systems: Windows, Linux

SKILL SET:

Xilinx Tool Flow (Xilinx ISE and Vivado Design Suite)

Creating a Project until Implementation

Xilinx FPGA Architecture (Virtex 5)

Knowledge on

Logic Resources

Interconnect Resources

Memory and DSP

Clocking Resources

Clock Management

FPGA Design Techniques

Synthesis Techniques

Global Timing Constraints

Static Timing Analysis

ASIC design flow

ASIC verification

Physical design

FPGA Platforms Used:

Xilinx : Spartan 3e, Virtex 5, Zynq 7000, (Zed board and Zybo board) Altera : Altera DE2-115 (Cyclone IV)

PROJECT ACTIVITIES:

TITLE 1: DESIGN OF AX14 FIFO

FEATURES:

FIFO Data Width From 1 to 4096 Bits

Supports all 3 AX14 Interface Protocols

Configurable Fully Empty Flags

Configurable Interrupt Signals

Selectable Memory Type

TITLE 2: Optical Object Counter

The system comprises IC1 and IC2 and H22LOI sensors to detect the object when it passes by.

TITLE 3: Dynamic Voltage and Frequency Scaling for mobile devices DVFS technique is employed to reduce the power consumption of mobile devices by increasing the access time of the device. It is performed with the help of PIC 16F877 controller in the system.

TITLE 4: Design of an area efficient adder using minority gates in QCA The Quantum-dot Cellular Automata (QCA) approach represents one of the possible solutions in overcoming the physical limit of transistors. The proposed adder outperforms all state-of-the art competitors and reduces area-delay efficiently than previous designs. CO-CURRICULAR ACTIVITIES:

Participated in in-plant training conducted by BSNL.

Active member of NSS.

Attended two day workshop on “Solid State Device Modelling and Simulation” held at KPR Institute of Engineering and Technology.

PROFESSIONAL SKILLS:

Decision making

Team player

Conceptual Skills

STRENGTH:

Flexible

Working as a team

Extrovert

HOBBIES:

Listening to music, playing football and cricket, travelling, gardening and interaction with people. PERSONAL PROFILE:

Date of birth : 17-02-1992

Languages known : English, Tamil

Address : #4,Mohana apartment,

(opp to venkateswara coll)

Thaverekere road, Madiwala,

Bangalore,

Karnataka-560068

DECLARATION:

I hereby declare that the information furnished above is true to the best of my knowledge and belief.

Abilash.B

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