| Distance: | Job alert | Jobs 161 - 170 of 1430 |
US_West Electrical / Electronics & Semiconductors Engineer_L3
Datum Technologies Group
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Santa Clara, CA, 95053
... Good knowledge of Verilog and scripting languages (Tcl and Python preferred). "All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, ... - Aug 24
ASIC Engineer Remote )
TALENTPRO CONSULTING, INC
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Baltimore, MD
... • Knowledgeable in VHDL, Verilog or System Verilog RTL coding and highly proficient in DFT methodologies. • Responsible for operating in a team environment and collaborating across the different teams as required to accomplish the goals. Basic ... - Aug 04
Design Verification Engineer
Tekfortune Inc
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San Francisco, CA
... Role: Design Verification Engineer Location: Bay Area, CA Duration: 6+ Months Required Skills: Design Verification, ASIC, Verilog, UVM Job Description: Rich experience in constructing highly scalability, configurability, and reusability DV ... - Aug 04
Senior Staff Design Verification Engineer
Arteris IP
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Rollingwood, TX, 78716
... Triaging Regressions, Debugging RTL designs in Verilog and System Verilog. Help improve and refine verification process, methodology, and metrics. UVM expertise on complex SoC projects from test bench development to verification closure. Provide ... - Aug 23
DSP Application Engineer
Annapolis Micro Systems
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Parole, MD, 21401
100000USD - 200000USD per year
... Design Tools Experience with Matlab / Octave Experience with C/C++/Java, with experience in graphics Experience with VHDL or Verilog Experience in OpenVPX, PCIe, VME/VXS Experience with various communication protocols including Ethernet / Infiniband ... - Aug 24
RTL Design Engineer
ZipRecruiter
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Santa Clara, CA, 95053
... Job Description Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We're looking for a seasoned RTL engineer with 7+ years of experience in #RTLDesign #Verilog #VLSI #CDC #STA #Synthesis #DFT #Python ... - Aug 24
MLA IP Design Verification Engineer, Annapurna Labs
Amazon
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Cupertino, CA
$129,800-$212,800/year
... 3+ years of design verification experience using System Verilog and UVM 3+ years of experience in testbench development including: stimulus, checkers, assertions and coverage Experience verifying multiple levels of logic including: IP blocks and ... - Aug 23
CPU Design Verification Engineer
Apple
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Santa Clara, CA, 95053
... Being already familiar verification environments such as UVM and System Verilog will come a long way with us. Apply knowledge of industry standard interfaces and have a deep understanding of Verilog, Verilog simulator, and debuggers. Have a detailed ... - Aug 24
Emulation Validation/Verification Engineer
eTeam
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Santa Clara, CA, 95053
... • DV Experience: Design verification knowledge and experience with UVM/System Verilog • Debugging skills with waves and logs • Experience using zebu platform • Comfortable with C++ code implementation and handling • Proficiency with hardware ... - Aug 24
Sr Electronics Engineer
Rapiscan Systems
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Billerica, MA, 01821
... Develop HDL code using tools such as Active-HDL by ALDEC and applying applicable standards for VHDL/Verilog. Prepare product documentation such as interconnects, schematics, wiring diagrams, PCB Layouts, Assembly Drawings, BOMs, etc. Interpret ... - Aug 23