Design Verification Engineer

Tekfortune is a fast-growing consulting firm specialized in permanent, contract & project-based staffing services for world's leading organizations in a broad range of industries. In this quickly changing economic landscape, virtual recruiting and remote work are critical for the future of work. To support the active project demands and skills gaps, our staffing experts can help you find the best job for you.

Role: Design Verification Engineer

Location: Bay Area, CA

Duration: 6+ Months

Required Skills: Design Verification, ASIC, Verilog, UVM

Job Description:

Rich experience in constructing highly scalability, configurability, and reusability DV/Performance verification environment.

Experience in ASIC design/verification related field in IP, Subsystem or SOC level

Experience in writing System Verilog and/or System C models for simulation

Working experience in writing UVM models, checkers, and stimulus, constructing UVM register models and applying constrained random methodology in UVM test environment and stimulus

Compose test plan and validation vectors to ensure functional completeness

Experience with design for verification (assertion-based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)

Versatile in any one of the high-level verification flows such as SV,UVM, C++ etc. as well as knowledge of industry standard tools for verification

Excellent communication skills (both written and oral)

Strong problem-solving skills

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