| Resume alert | Resumes 51 - 56 of 56 |
Design Engineer
Pune, MH, India
... Projects in College: • Stop Watch: Implemented stopwatch code on FPGA. Coding of the stopwatch was done in the Verilog Language. It could count up to 999. It had many modules, namely, a 1 sec pulse timer,4 bit up/down counter, which was used in a 12 ... - 2012 Jun 14
... Projects in College: • Stop Watch: Implemented stopwatch code on FPGA. Coding of the stopwatch was done in the Verilog Language. It could count up to 999. It had many modules, namely, a 1 sec pulse timer,4 bit up/down counter, which was used in a 12 ... - 2012 Jun 14
vlsi,asic,fpga,verilog/ vhdl
Pune, India
... MINI PROJECTS (CDAC): 1)Lcd interfacing with cpld xc9572 and fpga spartan 3e. 2)RTC design 3)Stepper motor interfacing with cpld xc9572. 4)ADC interfacing with cpld xc9572. 5)Seven segment multiplexing. 6)Traffic light controller MAJOR PROJECT (B.E) ... - 2012 Feb 13
... MINI PROJECTS (CDAC): 1)Lcd interfacing with cpld xc9572 and fpga spartan 3e. 2)RTC design 3)Stepper motor interfacing with cpld xc9572. 4)ADC interfacing with cpld xc9572. 5)Seven segment multiplexing. 6)Traffic light controller MAJOR PROJECT (B.E) ... - 2012 Feb 13
Pvt Ltd System
Pune, MH, India
... SEMINAR Seminar on “DSP ENHANCED FPGA”at R.C.Patel institute of technology,shirpur. TRAININGS / CERTIFICATIONS “Embedded System”by Microsoft IT Academy,Pune. AREA OF INTEREST Embedded System Programming. Pcb designing. Telecommunication. EXTRA ... - 2012 Jan 08
... SEMINAR Seminar on “DSP ENHANCED FPGA”at R.C.Patel institute of technology,shirpur. TRAININGS / CERTIFICATIONS “Embedded System”by Microsoft IT Academy,Pune. AREA OF INTEREST Embedded System Programming. Pcb designing. Telecommunication. EXTRA ... - 2012 Jan 08
Software Engineer
Pune, MH, India
... But in advanced to make life long we are using FPGA. Responsibilities:- 1) Software Development In VHDL 2) Design of PWM Circuit ACDEMIC PROJECTS (Jan 2009-jun 2009) Project Name: “Display Real Time Clock with Calendar and Alarm’ In Kiel software ... - 2011 Aug 11
... But in advanced to make life long we are using FPGA. Responsibilities:- 1) Software Development In VHDL 2) Design of PWM Circuit ACDEMIC PROJECTS (Jan 2009-jun 2009) Project Name: “Display Real Time Clock with Calendar and Alarm’ In Kiel software ... - 2011 Aug 11
Manager Engineer
Pune, MH, India
... Attended Training Programme on ‘(Field programmable Gate Array) FPGA Implementation ’ conducted by C-DAC’s Soft Polynomials,Nagpur. ACADEMIC PROJECT UART ‘Universal Asynchronous Receiver & Transmitter’ PLATFORM USED–VHDL DESCRIPTION- The ... - 2010 Oct 19
... Attended Training Programme on ‘(Field programmable Gate Array) FPGA Implementation ’ conducted by C-DAC’s Soft Polynomials,Nagpur. ACADEMIC PROJECT UART ‘Universal Asynchronous Receiver & Transmitter’ PLATFORM USED–VHDL DESCRIPTION- The ... - 2010 Oct 19
PCB Design Expert
Pune, India
... SI constraints board with FPGA, and Processor chip. PTC Software: • Working as Engineer II • Worked on ECAD-MCAD Collab mode. Between Product view /ProE/InterComm Expert • Creating schematic in Orcad schematic capture, Dx designer. • Creating layout ... - 2010 Aug 22
... SI constraints board with FPGA, and Processor chip. PTC Software: • Working as Engineer II • Worked on ECAD-MCAD Collab mode. Between Product view /ProE/InterComm Expert • Creating schematic in Orcad schematic capture, Dx designer. • Creating layout ... - 2010 Aug 22