Software Engineer Project

PRIYA

***** **** **** **** *** # **D, Irvine – **612, California, U.S 949-***-**** *****.*****@*****.***

EXPERIENCE SUMMARY

I was working as a Project Lead with Atrenta Inc. as. Previously worked with Infogain Technologies, Noida, as a Software Engineer. Having an accumulated work experience of 6 yrs in the areas of

o ASIC/FPGA Design

o Review of Functional and Test Specifcations

o Creation of Technical Design Specification and review of design created by peers

o Coding and code reviews

o Mentoring new recruits

AREA(S) OF EXPERTISE

Proficient in VHDL, Verilog, C, C++, Perl, OOPS concepts.

Experience in System Verilog

Worked extensively on design and development of policies for Starc2005

End to end delivery responsibility of custom policies of Texas Instrumentation, Qualcomm, STM, Samsung, etc.

Exposure of verification through directed and random tests.

Exposure of detailed test planning at block and system level to verify the hardware implementation of the design

Redesigned automation scripts to suit the needs of base policies team

Create and analyze coverage metrics to ensure code coverage

SKILLS

(Domain//Languages/Tools)

Languages: C, C++, Perl, System Verilog, VHDL, Verilog, OOPS concepts.

Development Tools: GCC, VIM, Simulation tools (Modelsim, NC-Verilog, VCS)

Optimization Techniques: Gdb, Valgrind, Gcov

OS: Red hat Linux

EDA Tools: DC, Spyglass

Version control tools: CVS

EDUCATION

Degree/Course Level School & Board/University Aggregate Year

10 B.N. Public School, C.B.S.E 80.8% 1998

10+2 M.V.N Sr. Sec. School, C.B.S.E 90.6 % 2000

Bachelor of Technology (equivalent of BS),

Instrumentation & Control Engineering Netaji Subhas Institute of Technology (NSIT), Delhi University

Tier 1 Engineering college in India

75.71% 2004

AWARDS AND DISTINCTIONS

• Awarded Certificate of Merit (Science) by CBSE in 1998 for being in top 0.1% (35000 candidates)

• Secured highest PCM (Physics/Chemistry/Mathematics) (96.5%) in Grade 10th in the school.

• Secured highest PCM (Physics/Chemistry/Mathematics) (96%) in Grade 12th in the school.

• Secured 212(Outside General-OG) rank in DCE CEE, 391 rank in PEC, 51(OG) in IGPSU.

• Received scholarship for the year 2001-2002, 2002-2003 for being in top students in the institute.

PROFESSIONAL EXPERIENCE

December 2004-August 2010 (5 Years 8 Months) - Atrenta Inc. Designation –Project Leader

Domain

EDA - Electronic design automation by providing a suitable platform that captures, aggregates, and apply knowledge and constraints critical for correct and efficient design. The knowledge and the constraints are captured in the form of rules.

Job responsibilities

• Managing a team of five

• Development and Release of customer specific policies for selected clients.

This involved development from scratch in the following phases:

i) Requirement analysis,

ii) Project scheduling and delivery of technical specifications

iii) Implementation based on the customer’s inputs on the technical specifications

iv) Quality analysis followed by product delivery

v) Operation and maintenance.

• Preparing Technical design of interactive and incremental SpyGlass® rules

• Product support and enhancement for SpyGlass® software

• Mentorship of the new recruits to Atrenta Inc. This included training programs, assistance on crucial tasks and work reviews.

• Part of the core team responsible for migration of existing policies code to the new architecture of the SpyGlass software. Quality Analysis and internal releases for the same

Project #1: Lint and Good Design Practices Methodology

I was responsible for the rule writing and bug fixing of this methodology. The major task was to fix any bugs or errors related to width mismatch, tristate logic, functional issue due to improper coding, Clock and Reset problem in the given RTL. The methodology included a set of coding guidelines and rules to enforce good design practices.

Skills: C, C++, Perl, Verilog, VHDL

Project #2: Custom policies development

I was responsible for the development of a few custom based policies of customers like Qualcomm, Broadcom, Samsung, Intel and TI. These work of these policies included the customization of RTL, FLAT and NOM related rules.

Skills: C, Perl, Verilog, VHDL

Project #3: SystemVerilog (IEEE1800-2005 ) related enhancements in SpyGlass

• Involved to provide the complete SV support at policy end in four phase.

• Reviewing testplans for every phase of implementation.

• Providing the system verilog support in the C/C++ code

• Design & Verification construct support were provided separately.

• Supported constructs were tested based on small unit test cases and big designs.

• SystemVerilog based on Beacon Test suite validated for Spyglass.

• Fixed and verified many customer issues

Skills: C, Perl, System Verilog

Project #4 :

• Migration of policies to the new system environment.

Skills: C, VHDL

August 2004 - December 2004-Infogain Pvt. Ltd. – Software Engineer

EXTRA CURRICULAR ACTIVITIES

• Organized cultural and game shows in annual college festival, also won prizes in various athletic events like 100m, volleyball, shot put

• I won first prize in Atrenta Inc’s Ping Pong championship

• I was secretary of Atrenta Inc’s Event Management Group while holding this post I organized and participated in various team building and motivating events

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