Project Engineer
Resume:
PRASAD M. PARIMI
********@*****.*** – US citizen.
OBJECTIVE: A challenging position in Program (Project) or Foundry Management in the development of new products.
PROFESSIONAL EXPERIENCE / SKILLS:
o Experienced in semiconductor industry in program/project Management, process technology development and foundry operations.
o Over 8 years of unique Technical Project Management experience in both Physical IP (library)
and ASIC (networking) products development.
o Experienced in working with biggest off-shore foundries and cross functional product
development teams.
o Excellent in written/verbal communication, inter personnel, problem solving, negotiation,
presentation, people and analytical skills.
o Skilled at identifying/tracking critical nodes and risk management
o Result oriented with self-motivation, technical and organizational skills.
o Power user of Plan View, RS/1, MS Project, MS Office, Power Point, Data Power, SAP, Siebel, FMEA and Six Sigma techniques.
Consultant (2010-current)
o Working with a private firm to establish a solar farm in Asia.
o Created business plans for venture capital, defined product strategy, technology selection, infrastructure requirements, organization establishment, operations execution etc., plans.
BiCMOS Foundry, Santaclara, CA
Operations Program Manager (2008-2010)
o Optimized the process flow and improved the efficiency of equipment usage. Reduced the excess material handling, improved cycle time and yield of current/new high volume products.
ARM (Artisan) Corp, Sunnyvale, CA
Principal Program Manager (2002-2008)
o Managed deployment of over 15 custom Physical IP libraries (Standard cells, Memories, I/Os and Specialty I/Os, test chip) to top wafer manufacturing foundries including IBM, Chartered, Samsung, Fujitsu, NEC etc., on schedule for technologies ranging from 0.13um to 45nm.
o Served as primary point of contact for customers for effective communication through the entire product life cycle for day-to-day operations, technical and customer related interactions and as a liaison between internal teams: engineering, software, sales, marketing, finance and legal.
o Worked closely with marketing (pre-sales) in winning new products by providing product feasibility summaries, project budgeting and scheduling. Worked closely with engineering teams to estimate effort of product customizations. Used earlier experience to validate ROI estimates.
o Met over 90% of delivery schedules by establishing realistic scope, objectives, project plan, project milestones and schedule for all projects. Built the credibility with customers by managing timelines, critical milestones, dependencies, priorities and requirement changes.
o Abel to prioritize among many conflicting needs and advocated a course of action. Translated customer requirements into product specification and specific tasks in project plan.
o Proactive risk manager who identified risks and established mitigation/contingency plans, reduced one major project delay by more than 3 months.
o Led global cross-functional teams, engineering, software, technology development and test chip at CA, TX and India to execute plans as per product life cycle with quality.
o Organized weekly teleconferences with customers and communicated progress reports consistently.
o Communicated to management in monthly executive meetings about project status and influenced for portfolio changes, resource allocations and task force creations.
o Generated over $1M in revenue by regulating change control, negotiated scope and time adjustments with partners and stakeholders, when necessary.
o After product release, worked with engineering in resolving any bugs informed by customers.
Prasad Parimi(continued) Page 2
o Worked with test chip group in designing the test chip with customer embedded IP, testing the device, creating the report and failure analysis of any particular module. Used my prior experience in semiconductor technology to resolve any technical issues.
o Proficient in QA and release of products to customers, web and communication of release notifications. Attended several Project Management courses and training classes.
LSI LOGIC CORP, Milpitas, CA (1989-2002)
Technical Program Manager- Networking Division (2000 - 2002)
o Coordinated cross functional teams for the development of high technology networking products
from the delivery of net list to proto evaluation on board.
o Managed 11 very complex ASIC designs starting from RTL to prototype delivery / board
evaluation having a potential of about $250M in product lifetime revenues.
o Managed development of leading and high revenue potential ASSP product, 24 port 10/100 Mbps two 1G Uplink layer2 Ethernet switch.
o Translated customer requirements into specific tasks for functional areas, initiated development
of DDR, CAM, new FPBGA HP packages, ATE hardware and specific custom cells for the
successful and timely completion of designs.
o Initiated project planning/schedules, tracked milestones, executed contingency plans and reduced
cycle time on long pull design by 5 weeks. Organized weekly customer meetings, reviewed
net-list and sdf timing milestones, updated management in monthly executive meetings about
schedules, cost and revenue plans and prioritized resources on critical projects to meet schedules.
o Worked closely with sales, circuit designers, design, package and operations teams to resolve
technical and logistic issues. Established initial proto requirements, coordinated capacity plans
with foundry operations based on forecasts and delivered protos before schedule.
o Negotiated contracts with contract service providers, saved about $30K on one project,
monitored their progress, schedules and payments on SAP.
Staff Process Technology Integration Engineer (1995 – 2000)
o Instrumental in the development of 0.18um (G12) process technology, DRC rules and Spice models.
o Project leader and coordinated five groups, lithography, diffusion, metallization, plasma etching and CMP for the development of 0.18um technology
o Defined the project goals from design requirements, designed test vehicles and established
process tolerance limits.
o Implemented new process modules and correlated physical vs electrical parameters.
o Received several Quality awards.
Staff/Senior Process Development Engineer (1989 – 1995)
o Developed new process technologies for future product development, performed process optimization, implemented process transfers and improved yields
o Evaluated future generation equipment and implemented in manufacturing.
o Developed and implemented new lithography processes.
o Directed Quality Improvement Groups for several QIMs for process improvement.
GE INTERSIL, Santa Clara, CA
Senior Process Development Engineer
o Responsible for litho process development and process transfer.
TELEDYNE SEMICONDUCTOR, Mountain View, CA
Process Development Engineer
o Supervised Lithography and Plasma Etching Departments and initiated the development
of new processes.
EDUCATION:
Ph.D Electrical Engineering, Indian Institute of Technology, Bombay, India
M.S Applied Physics, Andhra University, Waltair, India.
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