Analog/Memory Layouts

Rajesh Reddy Tummuru

Mobile:91-903*******

******************@*****.***

OBJECTIVE:

Seeking a position to utilize my skills and abilities to become a successful professional in the field of Semiconductor and to work in an innovative and competitive world.

BRIEF PROFILE:

• Over 6 years of industrial experience in Analog Layout And Memory Layout in various technologies from 180nm to 22nm.

• Solid understanding of design rules and verification for Deep Submicron CMOS Processes and BICMOS Process.

• Experience with Debugging DRC and LVS decks

• Proficient in Device Matching, Parasitic Analysis, Electron Migration, and Isolation Techniques.

• Good knowledge on Latch up, Metal density, Shield, Antenna and ESD.

• Experiences with Cadence tools including Virtuoso schematics Editor, Virtuoso Layout, layout XL Editor, Lakeer, Assura/Calibre verification tools.

• Mentoring new hires with analog layout training.

• Experience in handling full layout from Floor planning till Tape out.

• Working knowledge of the data management software DesignSync.

Key products worked on:

Analog Front end (IP) for Voice application.

>Current Steering DAC.

Data convertors.

>14 bit(SAR ADC)

>16 bit(SAR ADC-Radiation Harden)

>16 bit(PIPELINE ADC)

CMOS LNA

EXPERIENCE/PROJECTS:

1. IBM India Pvt. Ltd http://www.ibm.com

November 2011 Till Date

EDRAM Macro and Test Chip Development

Technology: 22 nm, SOI technology

Role/Responsibility: Layout lead.

Handling full floor plan and doing layout for Sense Amplifier.

2. Texas Instruments India Pvt. Ltd http://www.ti.com

June 2006 Till October 2011

14-Bit ADC (SAR Architecture)(32 Channels).

Technology: 90 nm, CMOS technology

Role/Responsibility: Layout lead.

Handled full floor plan and done layout for ADC,CLK Generator, Refsys blocks, high speed serial interface(5GHz) and top level hookup.

16-Bit ADC (PIPELINE Architecture).

Technology: 180 nm, CMOS technology

Role/Responsibility: Layout Lead.

Handled full floor plan and done layout for Stage-1,Stage-56789, high speed serial interface(3.5GHz) and top level hookup.

16-Bit ADC (SAR Architecture)(Radiation Harden).

Technology: BICMOS(Lmin-0.60um,E Size:0.4x0.8um)

Role/Responsibility: Layout Lead.

Handled full floor plan and done layout for dac and top level hookup.

LNA-VCA(32-Channel)

Technology: BICMOS(Lmin-0.60um,E Size:0.4x0.8um)

Role/Responsibility: Layout Lead

Handled top floor plan, layout for VCA block, IO-Ring, full chip

handling.

12-Bit ADC (PIPELINE Architecture)(4 Channels).

Technology: 180 nm, CMOS technology

Role/Responsibility: Block Layout Designer.

Handled full layout of Sample and hold block.

Analog Complex I/O (CODEC for VOIP Applications)

Technology: 90nm,CMOS process.

Role/Responsibility: Module Layout Designer.

Handled layout of DAC(Current steering dac). Full responsible of module to fix

reliability issues(Base and Metal layers density issues at module level)

Analog Complex I/O for DSL Modem SOC

Technology: 90nm,CMOS process.

Role/Responsibility: Block Layout Designer.

Handled full layout of PLL,refsys..

DLL(Delay locked loop)

Technology: 180 nm, CMOS technology

Role/Responsibility: Block Layout Designer.

Handled full layout of DLL.

ACADEMIC PROFILE:

• Masters in Micro-Electronics from Birla Institute Technology and Science, Pilani, Rajasthan, India.

• Diploma in Electronics from NTTF Electronics Training Centre, Electronics City, Bangalore, Karnataka, India.

TECHNICAL SKILLS:

Scripting Languages: Basic Knowledge of C,Pearl and Skill

Operating System: Windows, Linux, Sun Solaris.

Layout: Cadence Virtuoso, Virtuoso XL, Lakeer.

Verification Tools: ASSURA, K2VER, Calibre

PERSONAL INFORMATION:

Date of Birth: 24-04-1987

Sex: Male

Marital Status: Unmarried

Nationality:Indian

Place: Bangalore

Date: Signature [Rajesh Reddy Tummuru]

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