Oduru Mahesh

***,*** ******* ****,

Email: p0bpqg@r.postjobfree.com

Tirupati,A.P-517501.

Mobile: +918*********.

_______________________________________________________________________

Summary of Qualifications:

Good understanding of the ASIC and FPGA design flow.

Experience in writing test benches in System Verilog.

Very good knowledge in verification methodologies like UVM.

Experience in using industry standard EDA tools for the front-end design and

verification.

VLSI Domain Skills:

HDL

HVL

EDA Tool :

:

:

Domain

:

Knowledge :

Verilog.

System Verilog.

Questa Simulator, Aldec Riviera simulator

Modelsim and ISE simulator.

ASIC/FPGA Design Flow, Digital Design methodologies.

RTL Coding, FSM based design, Simulation,

Synthesis.

Professional Qualification:

BOARD/UNIVERSITY

YEAR

OF

AGGREGATE

COURSE

COLLEGE/

SCHOOL

STUDY

M.Sc

Staffordshire

University

Staffordshire

University,UK

2009-

2010

10/15

credits

B.TECH (ECE)

SRI VENKATESA

PERUMAL

COLLEGE OF

ENGINEERING &

TECHNOLOGY

JAWAHARLAL NEHRU

TECHNOLOGICAL

UNIVERSITY

2004-

2008

71%

Intermediate

Vikas Junior College

Board of Intermediate Ed.

2002-04

74.5%

VVN HIGH

SCHOOL

87.5%

SSC

BOARD OF

SECONDARY

EDUCATION

2001-

2002

Experience:

February’2012- present at Disalogic Micro systems Pvt ltd, Hyderabad.

Position: ASIC Verification Engineer.

November’2010- September’2011 at CVC Pvt.ltd, Bangalore.

Position: ASIC Verification Engineer.

VLSI Projects:

Ethernet 10G/40G/100G Protocol – verification

HDL: Verilog

EDA Tools: Questa simulator and Aldec –Riviera simulator.

Implemented the Protocol using Verilog HDL independently.

Verified the RTL model using UVM.

Synthesized the design.

.

APB Protocol – verification

HDL: Verilog

EDA Tools: Questa simulator and Aldec-Riviera simulator.

Implemented the Protocol using Verilog HDL independently.

Verified the RTL model using System Verilog.

Synthesized the design.

I2C Protocol – verification

HDL: Verilog

EDA Tools: Questa simulator and Aldec –Riviera simulator.

Implemented the Protocol using Verilog HDL independently.

Verified the RTL model using System Verilog.

Synthesized the design.

Declaration:

I hereby declare that all the information furnished here in are true and correct to

the best of my knowledge and belief.

(MAHESH.O)

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