Project Engineer
Resume:
Prashanth Kumar Singh
Fremont, CA-94538, (Open to Relocation) *********.***********@*****.***
OBJECTIVE
Hardware design/test engineering position with skills matching my education & technical experience.
TECHNICAL SKILLS
Programming Language : C, C++, VHDL, Verilog, P-Spice, Perl Scripting
OS environment : Linux, Windows XP/Vista/7, Macintosh OS X, UNIX (Solaris).
Tool : EDA/Cadence Tools, Xilinx ISE, Modelsim, Allegro PCB Router, Allegro PCB Editor
Applications : Microsoft word, excel, power point; pdf.
WORK EXPERIENCE
California State University, Northridge
Research Assistant: May 2010 – Present
Member of Research group specializing in modifying Xilinx Virtex – 4 features under ASIC/FPGA Specialist Dr. Ramin Roosta, JPL,NASA,CA.
Analyzed and plotting schematic diagram of Virtex – 4 using Cadence Allegro tool which includes PCB Routing and Layout Editing. Designed Circuits and Verified.
Worked together with expert engineers to ensure the best quality and functionality testing of the fabricated board using different testing methods such as D- algorithm, IDDQ etc and writing code/ test cases in VHDL/Verilog for hardware & Performance Verification of the FPGA board.
Designed Communication protocol RS-232 on FPGA board using UART to drive the Virtex – 4 under a Dynamic burn-in platform and Verification of target board with traceability.
Teaching Assistant: May 2010 – May 2011
Duties include teaching Xilinx software, leading the Electronic circuit lab sessions. Tutoring C, digital hardware
testing, Routing, Component Placement, VLSI.
Grading assignment, assisting students in their project work, presented seminars lecture on hardware testing.
Mindteck Pvt. Ltd. (India) July 2007 – July 2009
Firmware Engineer:
Designed Control and communication board for an impressed current Cathodic Protection Rectifier (CPR) Module based on CYCLONE FPGA and Electrochemical cell. Also involved in technical documentation.
Basic knowledge on L2 Switching/ L3 Routing: - which deals with LAN which includes hubs, bridges, switches and different types of LAN Ethernet, Token Ring, and FDDI. Using Routing technique for sending the Data packet across geographically different location.
Worked on the project to consolidate existing PepsiCo servers into data centers, by remotely logging to the virtual or physical servers on Unix/Linux, Interface virtualization for servers with virtual machines, QA process, Allocation of storage and backup, Creation of users and provide user rights, required applications, Assigning of NIC address.
ACADEMIC PROJECTS
• Testing and Testability of Virtex-4 FPGAs
Designed a fully programmable hardware/software platform that allows dynamic burn-in test of Virtex-IV FPGAs, Conducted speed test, memory test and performance test using Xilinx development board.
Xilinx Virtex-IV FPGA is tested under high temperature stress by placing it in an oven @ 125 C while it is powered on and configured to perform a certain function. The test vectors are applied to the chip and the response is collected.
Tested the whole Block RAM and distributed RAM by writing test codes which will write random values to all memory addresses locations and then read from each a particular memory location.
Established the communication between the Burn in board (FPGA Board) and Adapter board using the RS-232 interface.
• Block RAM based Average Calculator of 32 16-Bit Elements
Using main aspects of Computer Architecture, Designed state machines and interfaced it to the data path to find the average of 32 16-bit element arrays M stored in the memory using Control Unit, Data path and a State Machine.
Modelsim is used for simulation and Xilinx ISE 12 for the synthesis on-board using VHDL.
• Designed, built and tested an Arm Controlled Robot using an Embedded Web Server
Project included requirement analysis, implemented the web server using HTTP 1.1.
Designed ROBO functionalities and hardware using microcontroller.
Designed flow charts and DFD’s, Coded, tested and documented.
• Designed, built and tested a Network Monitoring system using GSM for control
Project included requirement analysis, applied SMS functionality of GSM/GPRS.
Used the concept of Network (TCP/IP) programming.
Designed the format by using SMS communication between the administrator and server, coding and testing the entire CAN network.
EDUCATION
Master of Science (MS) in Electrical Engineering May 2011
California State University, Northridge (CSUN)
Bachelor of Engineering in Electronics and Communication June 2008
Visvesvaraya Technological University, Bangalore, India
RELEVANT COURSEWORK
FPGA/ASIC Design using VHDL Computer Architecture Diagnosis/Reliable Design of Digital s
Design Automation of Digital Systems Microprocessor & Microcontroller Computer Communication Network Computer Organization Verilog for Digital Integrated Circuit Programming in C and C++
Digital Signal Processing Electronic Circuits & Logic Design Analog Circuits
PROFESSIONAL TRAINING
Cadence Editing and Routing Workshop CSUN, CA 2010
Undergoing internet course training on PCB editing and routing called Allegro PCB Editor Basic Techniques v16.2 and Allegro PCB Editor Intermediate Techniques v16.2
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