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Electrical Engineering, Power Engineering

Location:
Seattle, WA
Posted:
July 16, 2012

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Resume:

Hongyou Chen

**** *** *** **, ******* WA *****

206-***-****

******@**.***

Objective

I am seeking for an internship or full time job opportunity at Pulp $ Paper as a Power engineer that will utilize my strong work ethic and communication skills while simultaneously developing my technical abilities.

Skills and Strengths

• Excellent knowledge in Verilog circuit design, FPGA research experience

• Five quarter of Control Theory and Power System courses at University of Washington.

• Strong analytical skill in various System Schematic Diagrams as well as System Load analysis.

• Solid understanding of EMS, network applications, power flow applications

• Two quarter java programming course, three years of Matlab experience.

Education:

University of Washington Seattle, WA

Current Major GPA 3.53/4.0

Major:

Electrical Engineering Expected Graduation: June 2012

Concentration: Large Scale Power System and Sustainable Energy

Project & Experience

EEG project, for Professor Dabiri, DanaKey

Involved in EEG (electroencephalogram) project. With the help of open source site, I along with a graduate EE student managed to build and design a simple but reliable version of EEG. Responsibilities includes building the 16 active electrodes, remodeling the analog board design base on the schematics diagram, that provide on the open source site, eliminating the noise that generate from and pick up by active electrodes and transmission section between analog board and digital board.

Electrical Drive Design project(EE453)

Project for my senior Capstone class, involved in building an electrical controlled motor to meet various design specification: Bi directional, Speed Control, Counter Current braking and dynamic braking. My main duties in the team: programming Arduino Uno Microcontroller to control all the specifications.

Research position at Wireless and Sensor lab

Main objective: Utilize DE2 FPGA board to implement a testing platform for Bit-error-rate of our receiver chips. Other responsibilities involved: implement additional modules such as noise generation, display the bit error rate on seven segments Hex display board, and utilize Verilog to design logic circuits.

Pacific Northwest ISO’s Transmission System Upgrade project(EE454)

Based upon the data and requirements outlined by the Western States System Operators Coalition that provided by instructor, me and my group carefully analysis Pacific Northwest ISO’s existing transmission system, came up necessary upgrade alternatives and recommended the best option to maintain a high stability margin for ISO as requested. Various duties assigned: transmission reliability margin (TRM) and Total Transfer Capability (TTC) analyzing, maximum social welfare argument: chosen safety margin was computed based on the creditable load and generation predictions.

Award &

Activates

• Dean’s list at University of Washington,Autumn2009, Autumn 2010, and Spring 2011

• Member of IEEE student branch at University of Washington, Since 2009

• National honor society. Shadle Park high school, Spokane WA 2007

• Elite Senior High School student Club, 2005 - 2007

• Saxophone, Level 7 Certificate, played in high school band.



Contact this candidate