Project Manager Engineer

Stanley Hsu (Shao-Ta Hsu), Ph.D.

**** *. *** ***** ** #102 Boise, ID 83716 ● 208-***-**** ● ********@*****.***

Principal Engineer / Project Manager

PROCESS DEVELOPMENT ~ R&D ~ CHEMICAL VAPOR DEPOSITION

Qualifications Profile

•Advanced talents in process development with specialization in plasma-based dielectric CVD (PECVD) for amorphous Si, Low k, barrier, ashable hard mask (AHM), DARC, IMD, HDP and STI films. Also well-versed in non-plasma-based for SACVD gap fill.

•Proficiency in using most-up-to date Integrated Circuit technology from 90 nm in 2004 to most recently 20 nm.

•Equally adept in both R&D and manufacturing environments in the United States and Asia.

•Professional achievements include 10 U.S. patents, three technical papers, and nine conference papers.

•Extensive CVD expertise spans PECVD/amorphous Si, PECVD/Carbon HM – AMAT APF and NVLS AHM, SACVD process (TEOS/O3), PECVD/SiON, and WCVD.

•Successfully launched first Cu mass production line of Taiwan from R&D to production mode.

•Consummate strengths in Low k Cu technologies encompassing SiC process– NVLS 4MS / NH3; 4MS / CO2 and AMAT 3MS/NH3 SiC Black Diamond: AMAT 3MS/O2 based for IMD.

•Championed SiH4 dep./ NF3 etch (in-situ DED) process to become 65nm STI baseline for United Microelectronics Corp.

Professional Experience

Micron Tech USA, Boise, ID, 06/2008 to Present

CVD Process Development Engineer – Micron Side/DRAM

•Spearhead cutting-edge CVD process development at Micron Fab 4 including seamlessly steering transition from oxide mold to amorphous silicon material for 1x nm Capacitor stack to enable higher aspect ratio capacitors.

•Plan, evaluate and develop carbon hard mask process with an emphasis on high pattern density/double patterning for 1x nm DRAM.

Project Manager – Nanya Side/Thin Films

•Maximized quality control and assurance by closely partnering with senior management at Nanya headquarters to facilitate and expedite problem solving efforts related to DRAM films.

•In role as Process Lead, directed, motivated and supervised Nanya Thin Films team at Micron site including high k, diffusion, CVD and sputter divisions.

Nanya Tech. Corp., Taipei, Taiwan, 04/2007 to 06/2008

Project Manager – Research and Development

•Actively supported R&D activities by driving new technology development for 48 nm DRAM Cu line evaluation.

•Critically assessed new Cu line tool arrangement and cost for 48 nm DRAM to ensure feasibility.

United Microelectronics Corp., Tainan, Taiwan, 07/2004 to 04/2007

R&D Principal Engineer / STI Loop Coordinator

•Enhanced module integration of 45 nm STI gap fill using SACVD process/steam anneal to form seamless gap fill and improve CMP/wet etch leveling for device leakage.

•Overcame manufacturing challenges associated with multi-step in-situ dep-etch-dep HDP CVD gap fill process for (AR~6 for 90 nm width & 530 nm depth) STI to achieve first worldwide application in 65 nm manufactures for in-situ dep-etch-dep HDP.

•Implemented five-step DEDED clipping free gap fill process in 65 nm, effectively overcame manufacture particle high, and extended MWBC x2 by pre-coat optimization.

•Analyzed and improved faulty silicon application by strategically facilitating high tensile/compressive PECVD Nitride CSEL layer development.

Taiwan Semiconductor Manufacture Corp., Tainan, Taiwan, 01/2000 to 07/2004

Principal Engineer – Fab 6 Thin Films Division

•Applied dynamic leadership talents toward establishing first Low k CVD production line and productivity expansion in Taiwan and provided extensive staff training in Low K technology.

•Proficiently developed and initiated new clean process for Low k film to rectify particle issue.

•Supported manufacturing personnel in fine-tuning CVD USG/SiON/FSG process by reducing and minimizing defects, maintaining SPC, improving tool efficiency, and controlling costs (i.e. NF3, 3MS, SiF4, gas).

•Set up key parts for facility alarm system to improve the high volume manufacture effeciency.

Principal Engineer – R&D Process Development & Transfer team

•Project-managed technology transfer for Low k IMD with Black Diamond and SiC blok etch stop layer by successfully creating all-on-one in-situ PreHeat/NH3 treat/SiC Cap process.

•Introduced seven-layer Low k Cu structure to successfully overcome challenging arcing/cracking/delamination issues.

•Discovered photo-chemical reaction and devised dark wet clean to support post-CMP clean.

•Resolved Cu peeling issue induced by environmental chemicals by introducing “N2 Mini environment control”.

TI-Acer Semiconductor Corp., Hsin-Chu, Taiwan, 07/1998 to 01/2000

Senior Engineer – R&D Process Development

•Actively contributed to and led CVD process development for 0.25 um/0.18 um logic including WCVD.

•Analyzed, planned, and resourcefully replaced TiN with SiON as a DARC layer on 0.18 um process.

Vanguard International Semiconductor Corp., Hsin-Chu, Taiwan, 06/1997 to 07/1998

Senior Engineer – R&D Process Development

•Played an integral role in CVD process development for 0.18 um DRAM.

•Replaced Locos process by implementing HDP CVD for STI/ILD.

Education

Ph.D., Material Engineering, Tatung University, Taipei, Taiwan, 1999

Master’s Degree, Material Engineering, Tatung University, Taipei, Taiwan, 1990

Bachelor’s Degree, Material Engineering, Tatung University, Taipei, Taiwan, 1988

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