Experienced Semiconductor Process Engineer

Anurag Yadav

**** * ********* **** ****, Mechanicsville, VA 23111 Cell 804-***-**** *********@*****.***

SUMMARY

• 5 years of work experience in semiconductor engineering operations with 4 years in very high volume semiconductor manufacturing industry.

• Experienced and detail knowledge of various semiconductor/PCB manufacturing processes i.e. Photolithography, Thin film deposition (Sputtering PVD), Electroplating, Anodization, and Wet Etching in class 100 clean room and class 10 FAB.

• Experience in Statistical methods of data analysis, problem solving using 8D methodology, SPC, FMEA, DOE, and FDC.

• Excellent written and verbal communication skills, proficiency and experience in creation of extensive technical documentation OCAP, SOPs.

• Strong project management and execution skills, experienced of technical presentations to PCRB/MRB forum, and training to technicians and sustainers.

EXPERIENCE

Photolithography Process Engineer (Semiconductor Manufacturing FAB)

Qimonda AG (Infineon Technologies) Sandston, VA 23150 April 2005 – March 2009

• Processes owner of photoresist coating and development tools, knowledge of Nikon steppers, ASML scanners and Metrology tools.

• Thorough knowledge of BRAC and photoresists chemistries and defectivity related to the resist, processes and tracks. Member of DIG teams for defect reduction and yield improvement.

• Optimized resist coating and development processes which resulted in chemical cost saving by half million dollars annually.

• Productivity improvement of photolithography process tools reducing speed loss in production, optimizing manufacturing flows, and improving tool uptime greater than 90%. Successfully completed litho tracks tool quals reduction and PM (preventive maintenance) optimization projects.

• Experience of monitoring process performance through SPACE charts and implementing/creating process control limits. Worked on the projects for improving and maintaining the Cpk, Cpl, and Cpu parameters for the critical lithography process layers.

Process Engineer (Internship), Xanodics Inc. and Research Assistant, University of Arkansas

700 Research Center Boulevard Fayetteville, AR 72701 (January 2003-January 2005)

• Fabricated Embedded Ta2O5 Capacitors on 150mm wafer (Glass, Silicon, and FLEX substrates) using Varian XM8 Cluster Sputter system (PVD thin film deposition tool) for dielectric as well as Top and Bottom metal layer deposition in Class 100 Clean room facility, anodized sputtered dielectric and patterned using the Karl Suss litho contact aligner and Wet etching process, fabricated contact pads for capacitor testing using Au and Ni plating.

• Electrical testing of fabricated capacitors for Leakage Current, Breakdown Voltage, Impedance.

• Used AFM and 4-point prober for surface analysis and electrical characterization of fabricated capacitors.

EDUCATION

Master of Science in Chemical Engineering GPA 3.90/4.00

University of Arkansas, Fayetteville, AR (August 2000 – August 2002)

Bachelor of Science in Chemical Engineering (August 1995 – August 1999)

RESEARCH

Defect Reduction and Failure Analysis of Anodized Ta2O5 integrated capacitors (Thesis)

Model Studies of Vickers-Zimmer Spooked-Wheel Polyester Finisher (MS Thesis CHEG)

• Developed Liquid Hold-up, Mass Transfer, Angle of Rise, Angle of Depression and Power Correlations for the Vickers-Zimmer Spooked-Wheel Polyester Finisher.

PUBLICATIONS

Yield and Reliability of Tantalum Pentoxide Integrable Decoupling Capacitors

37th International Symposium on Microelectronics, Nov. 14-18, 2004, Long Beach, California, IMAPS 2004.

Model Studies of Vickers-Zimmer Spooked-Wheel Polyester Finisher, W. Roy Penney and A. Anurag XVIII Biannual North American Mixing Conference June 24-29, 2001.

ACADEMIC HONOR

Eastman Fellowship Department of Chemical Engineering, University of Arkansas, Fayetteville.

SKILLS

Computer: JMP, MATHCAD, MATLAB, PRO-II, MS-Office, MS-Visio, MS Project, MS Access.

REFERENCES

Available on request.

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