Design Manager

Bruce K. Bates

Contact Info:

Cell phone: 408-***-****

Email: *******@*****.***

Technical Skills:

Experience in IC chip layout from floor planning through tape out in full custom analog and mixes signal mask layout

Expertise in digital, analog, and mixed signal circuits and standard cells in sub-micron technologies, the latest being TSMC 65nm, TI LBC8 & LBC7

Experience using Cadence Open Access, v 6.1.4, Virtuoso XL design tools, Assura, and K-2 verification tools. Also with specialized TI and Bosch tools.

Knowledge of Analog design flows for transistor level design of CMOS and BI-CMOS

History of improving space tolerances within a given technology

Supervised more junior IC Layout Designers-- provided direction and oversight along with technical guidance; prepared employee evaluations

Set up and manage remote design center in Colorado Springs, CO

Extremely well organized and detail oriented

Familiar with Unix and Linux languages.

Excellent communication skills

Proficient in Microsoft PC and Office environments

Senior Mask Layout Designer

Aug 2012 – Avago, San Jose, CA

Apr 2012 - Texas Instruments, Santa Clara, CA - TI LBC8 technology

Jan 2012 - Qualcomm, Santa Clara, CA – TSMC 28/40nm CMOS technology

2011 - Qualcomm, San Diego, CA – TSMC 65nm CMOS technology

2011 - Texas Instruments, Dallas, TX – Xfab xt018 technology – Medical Instruments

2011 - Bosch Automotive, Reutlingen, Germany – TI LBC8 technology

2011 - Texas Instruments, Dallas, TX – TI LBC7 technology

Full custom analog layout using Cadence Open Access, v 6.1.4 & 5.1.X – Virtuoso, XL design tools, Assura, and Calibre verification tools. Also with specialized TI and Bosch tools.

Senior Mask Layout Designer

Linear Technologies, Inc. Colorado Springs, CO

2007 to 2008

Full custom analog and mixed signal layout on Cadence Virtuoso and Cadence Virtuoso XL tools. DRC and LVS verification using Dracula and Assura tools.

Senior Mask Design Specialist

Agilent Technologies

Colorado Springs, CO

2006 to 2007

Full custom CMOS and Bi-CMOS layout design for high speed IC test technology using Cadence Virtuoso XL, Mentor Calibre, and Assura tools.

Senior Mask Design Specialist

Microchip Technologies, Inc.

Mountain View, CA

1996 to 2006

Innovative full custom analog and mixed signal layout on Cadence tools. DRC and LVS verification using Avanti/Hercules tools.

Set up remote design center in CO.

Senior Layout Designer

National Semiconductor, Santa Clara, CA

1995 to 1996

Full custom analog and mixed signal layout on Cadence tools. DRC and LVS verification using Dracula software.

Senior Layout Designer

Media Vision, Fremont, CA

1993 to 1996

Developed the IC Design Division at Media Vision, designing full custom analog and mixed signal layout on Cadence tools. DRC and L VS verification using Dracula software.

Design Manager

Sierra Semiconductor, San Jose, CA

1992 to 1993

Supervised senior Layout Designers while producing exceptional and innovative full custom mixed signal layout design in support of the Analog Design Group using Compass tools for layout, DRC and LVS verification.

Worked on improving ergonomic conditions for all layout designers.

Senior Layout Designer

Sierra Semiconductor, San Jose, CA

1986 to 1992

Full custom analog and mixed layout designs from schematic through tapeout. Many designs in support of R&D or product development efforts.

Community Involvement:

Linked In Profile: http://www.linkedin.com/pub/bruce-k-bates/11/509/892

Captain of Emergency Response Team, Teledyne Semiconductor

Head of the Architectural Control Committee, Bent Tree Community, Monument, CO. Developed web protocol for Bent Tree POA

Established local church web library and social interaction site while internet was in its infancy Announcer for both Laurelwood Swim Team and Junipero Serra Swim League Championship

Contributing editor Garden Railways Magazine and co-founder of AWNUTS train magazine

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