FPGA/VLSI Engineer - Smart Grid Protection

Keshav Sai Chowdary Kommineni

314-***-**** — ******.***********@*****.*** — LinkedIn: linkedin.com/in/keshav-sai/

Experience Summary:

•FPGA/VLSI Engineer with 3+ years of experience in FPGA design, RTL development, verification, hardware bring-up, and high-speed digital systems for industrial and embedded applications.

•Hands-on experience developing synthesizable RTL using Verilog, SystemVerilog, and VHDL for real-time processing and control applications.

•Experience implementing FPGA-based electrical protection functions, including over-voltage, under-voltage, over-current, short-circuit detection, and fault monitoring.

•Strong knowledge of industrial communication protocols, including SPI, UART, Ethernet, CAN, Modbus, AXI, and IEC 61850.

•Experience with real-time signal processing, digital filtering, harmonic analysis, power-quality monitoring, PWM generation, and motor-control applications.

•Skilled in FPGA verification using SystemVerilog/UVM, functional simulation, waveform debugging, assertions, and functional coverage.

•Hands-on experience with Xilinx Vivado synthesis, implementation, timing closure, ADC/DAC interfaces, DDR memory, AXI interconnects, and ARM processor integration

Skills

•Programming Languages: Verilog, VHDL, System Verilog, TCL, Bash/Shell scripting

•FPGA Tools: Xilinx Vivado, ModelSim, QuestaSim, Vivado Simulator

•Protocols: SPI, UART, Ethernet, CAN, Modbus, AXI, AXI-Lite, IEC 61850

•Verification Tools: QuestaSim, ModelSim, Vivado Simulator (Basic Debug), UVM

•Hardware Interfaces: ADC/DAC, DDR Memory, ARM Processors, GPIO

•Debug Tools: Oscilloscope, Logic Analyzer, Protocol Analyzer, Power Analyzer

•Operating Systems: Linux, Windows

Experience

•FPGA/VLSI Engineer - Schneider Electric: Location: Chichago, IL Jun 2024 to Present

Project: FPGA based Smart Grid Protection and Power Monitoring System Project Description:

Worked on FPGA and VLSI development for smart grid protection and industrial power monitoring systems used in energy automation platforms. Responsible for RTL development, high-speed data acquisition, real-time signal processing, and FPGA verification activities for electrical protection relays and power distribution control systems.

•Developed RTL modules using Verilog/SystemVerilog for real-time electrical signal-processing applications.

•Integrated FPGA-based communication interfaces using SPI, UART, Ethernet, and Modbus TCP/RTU with ARM/Linux software stacks, supporting IEC 61850 GOOSE communication for substation automation systems.

•Implemented FPGA-based relay protection logic for over-voltage, under-voltage, over-current, and short-circuit fault detection.

•Developed real-time digital filtering algorithms for power-quality monitoring and harmonic-analysis applications.

•Targeted Xilinx Zynq UltraScale+ FPGA platforms for real-time power-monitoring and protection applications.

•Implemented FPGA synchronization logic with GPS/PTP timing modules for microsecond-level event timestamping.

•Designed FPGA logic for SCADA data acquisition and remote-monitoring systems.

•Designed FPGA data-acquisition pipelines supporting multi-channel ADC sampling, DMA-based streaming, and DDR memory integration to optimize real-time voltage/current analytics and data throughput

•Performed FPGA synthesis, implementation, static timing analysis, and timing closure using Xilinx Vivado, resolving setup/hold violations and optimizing CDC paths.

•Developed SystemVerilog/UVM verification environments, including drivers, monitors, scoreboards, constrained-random sequences, assertions, and functional coverage.

•Performed FPGA board bring-up, high-speed signal validation, and hardware debugging using oscilloscopes, logic analyzers, protocol analyzers, and power analyzers.

•Developed TCL and Bash scripts to automate Vivado synthesis, implementation, and regression simulation flows.

•Reduced LUT utilization by 18% and improved processing latency through RTL pipelining and optimized BRAM allocation.

•Prepared design documents, validation reports, and technical-review presentations for engineering teams.

•FPGA Design Engineer - Medha Servo Drives-Hyderabad, India Jun 2021 to May 2022

Project: FPGA based Industrial Motor Control and Power Electronics Platform Project Description:

Worked on FPGA development for industrial motor control and power electronics systems used in factory automation and electrical drive applications. Responsible for RTL design, PWM controller implementation, high-speed communication integration, and FPGA verification activities for industrial automation platforms.

•Designed and implemented FPGA RTL modules using Verilog and VHDL on Xilinx Kintex-7 and Zynq-7000 platforms for industrial motor-control applications

•Implemented FPGA-based PWM generation and dead-time control logic for three-phase inverter and motor-drive applications.

•Integrated industrial communication protocols including CAN, SPI, UART, and Ethernet.

•Developed AXI4-Lite slave peripherals, custom FPGA register maps, and processor interfaces to integrate RTL modules with Zynq ARM processors for register configuration and real-time data transfer.

•Performed RTL simulation, functional verification, waveform debugging, and protocol analysis using ModelSim, QuestaSim, and Vivado simulation tools.

•Executed FPGA synthesis, implementation, and timing analysis using Xilinx Vivado tools.

•Developed FPGA-based fault-monitoring and protection logic for power-electronics systems.

•Integrated LVDS-based high-speed ADC/DAC interfaces for real-time current and voltage acquisition and sensing applications.

•Conducted FPGA board bring-up, hardware debugging, and system-level validation by integrating RTL modules with embedded firmware and PCB hardware components.

•Authored FPGA architecture specifications, timing reports, interface documentation, and validation test reports for engineering design reviews

Education

• Southern Illinois University Edwardsville:

Location: Edwardsville, Illinois, USA

Degree: Master of Science in Electrical and Computer Engineering GPA: 3.5/4.0

Aug 2022 to May 2024

• Karunya Institute of Technology and Sciences:

Location: Coimbatore, Tamil Nadu, India

Degree: Bachelor of Technology in Electrical and Electronics Engineering GPA: 3.31/4.0

Jun 2017 to Jul 2021

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