RTL Design & Verification Intern Candidate

KRISH PATEL

USA +1-201-***-**** *********@*****.*** linkedin.com/in/krish-patel-8361a62a1 github.com/krishasitpatel-tech SUMMARY

M.S. Electrical Engineering student targeting RTL Design, Physical Design, and Design Verification internships (CPU, GPU, SoC). Hands-on RTL-to- GDSII experience across synthesis, APR, and timing closure, including a GCN accelerator closed at ~667 MHz, 4.5 mW, 0.048 mm and a registered adder closed at ~3.3 GHz with 0 DRC/connectivity violations. Proficient in Verilog/SystemVerilog, UVM fundamentals, ASIC design flows, and functional verification.

CORE COMPETENCIES

• HDLs & HVLs: Verilog, SystemVerilog, VHDL

• Verification Fundamentals: UVM basics, testbench development, SystemVerilog Assertions (SVA), constrained-random & directed testing, functional coverage concepts, waveform debugging, Clock Domain Crossing (CDC) awareness, Linting

• Protocols: AMBA basics (AXI/AHB/APB), UART, I2C, SPI

• Digital & Computer Architecture: RTL design, FSM design (Moore/Mealy), ALU/datapath design, pipelining, memory controllers

• EDA Tools: ModelSim, Cadence Innovus, Synopsys Design Compiler, Cadence Virtuoso (Spectre/Layout), HSPICE

• Physical Design & Signoff: ASIC synthesis/APR, standard-cell layout, PEX, DRC/LVS, static timing analysis (STA), timing closure, FinFET/CNTFET fundamentals

• Programming & Scripting: Python (NumPy, SciPy, pandas), Tcl, Shell scripting, Embedded C, MATLAB

• Tools: Git, Linux/Unix

PROFESSIONAL EXPERIENCE

Design Verification Trainee Maxgen Technologies, India Jul 2024 – May 2025

• Assisted in developing block-level SystemVerilog testbenches to validate functional behavior of RTL modules under senior engineer guidance.

• Wrote and debugged directed and basic constrained-random test cases; helped identify and document RTL logic issues during simulation.

• Contributed to writing SystemVerilog Assertions (SVA) to check FSM state transitions and flag illegal states during simulation.

• Supported waveform analysis and bug triage using ModelSim, helping isolate root causes for design team review.

• Gained exposure to Clock Domain Crossing (CDC) checks and linting flows as part of RTL sign-off preparation. Embedded Systems Intern ACMEGRADE, India May 2024 – Jul 2024

• Designed and debugged embedded control systems using Arduino and sensors; validated system behavior through structured testing protocols.

• Implemented real-time control logic for sensor-driven applications, gaining practical exposure to hardware-software integration. PROJECTS

ASIC GCN Accelerator Implementation SystemVerilog · Cadence Innovus · ModelSim

• Designed and verified a GCN node-classification RTL module with FSM sequencing, memory access control, MAC datapaths, aggregation, and argmax logic.

• Completed full RTL-to-GDSII flow (synthesis + APR); closed timing at ~667 MHz with 4.5 mW power and 0.048 mm area.

• Generated GDS, SPF/SPEF, DRC/LVS, setup/hold timing, and power reports for final sign-off review. Verilog RTL Design Suite (FIFO, ALU, RTL Fundamentals) Verilog · ModelSim

• Designed a synchronous 8-entry, 9-bit FIFO with independent read/write pointer logic, register-array memory, and enable controls; verified wraparound and simultaneous read/write via structured testbench.

• Designed a parameterized 8-bit ALU with Half Adder, Full Adder, Carry Lookahead Adder, and Manchester Carry Adder blocks; validated functionality and timing via simulation and waveform debugging.

• Implemented a Binary Counter (74LS161-equivalent), Moore/Mealy FSMs for control sequencing, and a synchronous memory module, all verified through structured simulation.

2-bit Registered Adder ASIC Verilog · Synopsys Design Compiler · Cadence Innovus

• Designed RTL with input/output flip-flops and combinational carry logic; completed synthesis and post-route APR flow.

• Constrained to a 300 ps clock (~3.3 GHz); achieved post-route closure with +210 ps setup slack, 0 DRC violations, and 0 connectivity errors. Real-Time DSP Image Processing Embedded C · ARM Assembly · MATLAB · STM32

• Implemented four real-time image processing algorithms on STM32 using C and hybrid ARM Cortex-M assembly (LSR/LSL, LDRB/STRB loops, UDIV), achieving pixel-level processing at 128 96 resolution.

• Built a MATLAB serial-capture pipeline to stream live webcam frames, receive processed output, and display side-by-side results with histograms for real-time verification.

Additional Projects:

• Low Dropout (LDO) Voltage Regulator (Cadence Virtuoso/Spectre, TSMC 0.3 μm); OAI22 Standard Cell — Schematic, Layout & PEX (ASAP7); 8-bit ALU using CNTFET 32 nm.

EDUCATION

M.S. Electrical Engineering · VLSI & Computer Architecture Focus Arizona State University, Tempe, AZ Aug 2025 – May 2027 Coursework: Advanced Computer Architecture, Digital VLSI / ASIC Design, Functional Verification, Analog IC Design, VLSI Design Automation B.Tech. Electronics & Communication Engineering Pandit Deendayal Energy University, Gandhinagar, India Oct 2021 – May 2025 CERTIFICATIONS

Hardware Description Languages for FPGA Design University of Colorado Boulder (Coursera) Jan 2026 Microprocessor and Interfacing NPTEL (IIT/IISc) 2024

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