UVM AXI4 Verification Engineer
Resume:
Jialin Song
Education
Cornell University Ithaca, NY, USA • 08/2025 – 12/2026
Master of Engineering in Electrical and Computer Engineering Hebei University of Technology (HEBUT) Tianjin, China & Miami, FL, USA • 09/2020 – 06/2025 Bachelor of Engineering in Electrical Engineering and Automation
(This program is jointly provided by Hebei University of Technology and Florida International University,US) Technical Skills
Programming&Scripting:Verilog, SystemVerilog, VHDL, UVM, C/C++, python, Tcl, Perl, Makefile, shell Tools: ModelSim, VS Code, GTKWave, Klayout, Cadence, Matlab, Git, SVN, Cursor, Linux/Unix Protocals:AMBA(APB/AHB/AXI), UART, I2C, SPI
Methodology:Computer Architecture, OOP, Functional Coverage, Test Planning, LLM-driven Verification Assistance Experience
AXI4 On-Chip Interconnect Subsystem Verification 07/2024 – 06/2025 DV Intern at Hebei Puhua Technology Co., Ltd.
•Developed a modular UVM verification environment for 10+ AXI4-based IPs (multi-master crossbar, width converters, protocol bridges), enabling scalable reuse and reducing integration time to <3 days per IP
•Built a Python-based RTL static analysis tool to check reset naming conventions, AXI signal completeness, and strobe/data width consistency risks, integrated as a one-command Makefile target in the CI flow
•Created constrained-random stimulus targeting complex AXI scenarios (backpressure, burst interleaving, partial writes); debugged critical protocol issues including missing B-channel responses and incorrect SLVERR signaling via waveform and transaction-level tracing
•Implemented SVA protocol checkers for AXI-Lite payload stability on valid/ready handshakes, BVALID/RVALID drop detection, and configurable liveness timeouts; connected monitors to scoreboard via analysis ports for end-to-end data integrity checking
•Developed functional coverage models with cross-coverage on normal/error paths; built automated coverage hole classification to distinguish reachable vs. hard-to-hit bins from simulation logs, achieving >100% coverage across 500+ daily regression runs
•Built regression analysis and bug triage automation to parse multi-seed simulation logs, surface top failing signatures, detect flaky tests, and generate Jira-ready triage reports; all tools orchestrated via Makefile for one-command execution UVM-Based Verification of Ethernet MAC 04/2026 – 08/2026 Projects
UVM-Based Verification of 2-Way Set-Associative Cache for RISC-V
•Built a modular UVM testbench for a blocking 2-way cache RTL with val/rdy dual agents, reference model, and scoreboard; enabled automated regression via Questa scripts
•Developed directed and constrained-random tests covering hit/miss/refill/evict and corner cases; resolved protocol and data mismatches via waveform-driven debug
•Implemented SVA checkers bound to DUT for req/rsp type legality, val/rdy stall stability, and bounded latency on proc and mem request/response paths
•Built automated assertion review and coverage hole analysis tooling from simulation logs, with traceability-mapped test suggestions for unreachable bins
•Achieved >100% FSM coverage across 12 states and ~16 transitions; established testplan traceability mapping features to tests, assertions, and coverage points with automated broken-link detection UVM-Based Verification of Systolic-Array GEMM Accelerator
•Built a UVM verification environment for a 16 16 systolic-array GEMM accelerator, validating end-to-end dataflow across memory load, compute pipeline, and write-back stages
•Implemented a memory BFM and golden reference model with scoreboard-based checking for accumulation correctness and write-back ordering
•Enhanced constraint infrastructure with parameterized constraints and a scenario generator auto-producing multi-round cases across random, increment, stress-idle, and alternating-pattern modes
•Built a UVM subscriber-based coverage mapper consuming driver analysis port transactions, with coverpoints on scenario, idle, pattern, and seed band plus cross-coverage across scenario pattern idle
•Applied directed and constrained-random testing with functional coverage; debugged dataflow and pipeline issues via waveform analysis
APB Verification IP
•Independently developed a reusable APB VIP in SystemVerilog/UVM, delivering core components including interface, transaction, driver, monitor, sequencer, and active/passive dual-mode agent
•Added APB protocol checkers covering setup/access phase handshakes, pready/pslverr response legality, and illegal timing detection to enforce protocol compliance
•Built a scenario-driven sequence library with basic read/write, corner case, stress, and reset-in-middle scenarios to improve negative-path and robustness coverage
•Implemented APB timing SVA assertion templates with vacuity awareness to accelerate root-cause isolation during debug Strong candidate for ASIC design verification roles: SystemVerilog, UVM, SVA, AXI, Ethernet MAC, scoreboards, and constrained-random verification. ************@*****.*** 862-***-**** https://www.linkedin.com/in/jialin-song1/
•Built a modular UVM testbench for an open-source Gigabit Ethernet MAC, integrating AXI-Stream, AXI-Lite, and GMII agents with reusable drivers, monitors, and sequencers.
•Developed directed and constrained-random sequences for register configuration, packet transmission, reception, and TX/RX loopback across varying frame lengths and payload patterns.
•Implemented a CRC-32 reference model and end-to-end scoreboard to check frame data integrity and FCS correctness.
•Verified CRC error detection, short-frame handling, automatic padding, and inter-frame gap behavior through targeted test scenarios.
•Defined a verification plan and functional coverage points; integrated SVA protocol checks and regression testing to validate normal operation and corner cases.
RISC-V Verification Intern at Biio
Jialin Song
******@*******.*** 862-***-**** https://www.linkedin.com/in/jialin-song1/ Education
Cornell University Ithaca, NY, USA • 08/2025 – 12/2026 Master of Engineering in Electrical and Computer Engineering Hebei University of Technology (HEBUT) Tianjin, China & Miami, FL, USA • 09/2020 – 06/2025 Bachelor of Engineering in Electrical Engineering and Automation
(This program is jointly provided by Hebei University of Technology and Florida International University,US) Technical Skills
Programming&Scripting:Verilog, SystemVerilog, VHDL, UVM, C/C++, python, Tcl, Perl, Makefile, shell Tools: ModelSim, VS Code, GTKWave, Klayout, Cadence, Matlab, Git, SVN, Cursor, Linux/Unix Protocals:AMBA(APB/AHB/AXI), UART, I2C, SPI
Methodology:Computer Architecture, OOP, Functional Coverage, Test Planning, LLM-driven Verification Assistance Experience
AXI4 On-Chip Interconnect Subsystem Verification 07/2024 – 06/2025 DV Intern at Hebei Puhua Technology Co., Ltd.
•Developed a modular UVM verification environment for 10+ AXI4-based IPs (multi-master crossbar, width converters, protocol bridges), enabling scalable reuse and reducing integration time to <3 days per IP
•Built a Python-based RTL static analysis tool to check reset naming conventions, AXI signal completeness, and strobe/data width consistency risks, integrated as a one-command Makefile target in the CI flow
•Created constrained-random stimulus targeting complex AXI scenarios (backpressure, burst interleaving, partial writes); debugged critical protocol issues including missing B-channel responses and incorrect SLVERR signaling via waveform and transaction-level tracing
•Implemented SVA protocol checkers for AXI-Lite payload stability on valid/ready handshakes, BVALID/RVALID drop detection, and configurable liveness timeouts; connected monitors to scoreboard via analysis ports for end-to-end data integrity checking
•Developed functional coverage models with cross-coverage on normal/error paths; built automated coverage hole classification to distinguish reachable vs. hard-to-hit bins from simulation logs, achieving >100% coverage across 500+ daily regression runs
•Built regression analysis and bug triage automation to parse multi-seed simulation logs, surface top failing signatures, detect flaky tests, and generate Jira-ready triage reports; all tools orchestrated via Makefile for one-command execution UVM-Based Verification of Ethernet MAC 04/2026 – 08/2026 RISC-V Verification Intern at Biio
•Built a modular UVM testbench for an open-source Gigabit Ethernet MAC, integrating AXI-Stream, AXI-Lite, and GMII agents with reusable drivers, monitors, and sequencers.
•Developed directed and constrained-random sequences for register configuration, packet transmission, reception, and TX/RX loopback across varying frame lengths and payload patterns.
•Implemented a CRC-32 reference model and end-to-end scoreboard to check frame data integrity and FCS correctness.
•Verified CRC error detection, short-frame handling, automatic padding, and inter-frame gap behavior through targeted test scenarios.
•Defined a verification plan and functional coverage points; integrated SVA protocol checks and regression testing to validate normal operation and corner cases.
Projects
UVM-Based Verification of 2-Way Set-Associative Cache for RISC-V
•Built a modular UVM testbench for a blocking 2-way cache RTL with val/rdy dual agents, reference model, and scoreboard; enabled automated regression via Questa scripts
•Developed directed and constrained-random tests covering hit/miss/refill/evict and corner cases; resolved protocol and data mismatches via waveform-driven debug
•Implemented SVA checkers bound to DUT for req/rsp type legality, val/rdy stall stability, and bounded latency on proc and mem request/response paths
•Built automated assertion review and coverage hole analysis tooling from simulation logs, with traceability-mapped test suggestions for unreachable bins
•Achieved >100% FSM coverage across 12 states and ~16 transitions; established testplan traceability mapping features to tests, assertions, and coverage points with automated broken-link detection UVM-Based Verification of Systolic-Array GEMM Accelerator
•Built a UVM verification environment for a 16 16 systolic-array GEMM accelerator, validating end-to-end dataflow across memory load, compute pipeline, and write-back stages
•Implemented a memory BFM and golden reference model with scoreboard-based checking for accumulation correctness and write-back ordering
Jialin Song
******@*******.*** 862-***-**** https://www.linkedin.com/in/jialin-song1/ Education
Cornell University Ithaca, NY, USA • 08/2025 – 12/202 Master of Engineering in Electrical and Computer Engineering Hebei University of Technology (HEBUT) Tianjin, China & Miami, FL, USA • 09/2020 – 06/202 Bachelor of Engineering in Electrical Engineering and Automation
(This program is jointly provided by Hebei University of Technology and Florida International University,US) Technical Skills
Programming&Scripting:Verilog, SystemVerilog, VHDL, UVM, C/C++, python, Tcl, Perl, Makefile, shell Tools: ModelSim, VS Code, GTKWave, Klayout, Cadence, Matlab, Git, SVN, Cursor, Linux/Unix Protocals:AMBA(APB/AHB/AXI), UART, I2C, SPI
Methodology:Computer Architecture, OOP, Functional Coverage, Test Planning, LLM-driven Verification Assistance Experience
AXI4 On-Chip Interconnect Subsystem Verification 07/2024 – 06/202 DV Intern at Hebei Puhua Technology Co., Ltd.
•Developed a modular UVM verification environment for 10+ AXI4-based IPs (multi-master crossbar, width converters, protocol bridges), enabling scalable reuse and reducing integration time to <3 days per IP
•Built a Python-based RTL static analysis tool to check reset naming conventions, AXI signal completeness, and strobe/data width consistency risks, integrated as a one-command Makefile target in the CI flow
•Created constrained-random stimulus targeting complex AXI scenarios (backpressure, burst interleaving, partial writes); debugged critical protocol issues including missing B-channel responses and incorrect SLVERR signaling via waveform and transaction-level tracing
•Implemented SVA protocol checkers for AXI-Lite payload stability on valid/ready handshakes, BVALID/RVALID drop detection, and configurable liveness timeouts; connected monitors to scoreboard via analysis ports for end-to-end data integrity checking
•Developed functional coverage models with cross-coverage on normal/error paths; built automated coverage hole classification t distinguish reachable vs. hard-to-hit bins from simulation logs, achieving >100% coverage across 500+ daily regression runs
•Built regression analysis and bug triage automation to parse multi-seed simulation logs, surface top failing signatures, detect flak tests, and generate Jira-ready triage reports; all tools orchestrated via Makefile for one-command execution UVM-Based Verification of Ethernet MAC 04/2026 – 08/202 RISC-V Verification Intern at Biio
•Built a modular UVM testbench for an open-source Gigabit Ethernet MAC, integrating AXI-Stream, AXI-Lite, and GMII agents with reusable drivers, monitors, and sequencers.
•Developed directed and constrained-random sequences for register configuration, packet transmission, reception, and TX/RX loopback across varying frame lengths and payload patterns.
•Implemented a CRC-32 reference model and end-to-end scoreboard to check frame data integrity and FCS correctness.
•Verified CRC error detection, short-frame handling, automatic padding, and inter-frame gap behavior through targeted test scenarios.
•Defined a verification plan and functional coverage points; integrated SVA protocol checks and regression testing to validate normal operation and corner cases.
Projects
UVM-Based Verification of 2-Way Set-Associative Cache for RISC-V
•Built a modular UVM testbench for a blocking 2-way cache RTL with val/rdy dual agents, reference model, and scoreboard; enabled automated regression via Questa scripts
•Developed directed and constrained-random tests covering hit/miss/refill/evict and corner cases; resolved protocol and data mismatches via waveform-driven debug
•Implemented SVA checkers bound to DUT for req/rsp type legality, val/rdy stall stability, and bounded latency on proc and mem request/response paths
•Built automated assertion review and coverage hole analysis tooling from simulation logs, with traceability-mapped test suggestions for unreachable bins
•Achieved >100% FSM coverage across 12 states and ~16 transitions; established testplan traceability mapping features to tests, assertions, and coverage points with automated broken-link detection UVM-Based Verification of Systolic-Array GEMM Accelerator
•Built a UVM verification environment for a 16 16 systolic-array GEMM accelerator, validating end-to-end dataflow across memory load, compute pipeline, and write-back stages
•Implemented a memory BFM and golden reference model with scoreboard-based checking for accumulation correctness and write-back ordering
Jialin Song
******@*******.*** 862-***-**** https://www.linkedin.com/in/jialin-song1/ Education
Cornell University Ithaca, NY, USA • 08/2025 – 12/20 Master of Engineering in Electrical and Computer Engineering Hebei University of Technology (HEBUT) Tianjin, China & Miami, FL, USA • 09/2020 – 06/20 Bachelor of Engineering in Electrical Engineering and Automation
(This program is jointly provided by Hebei University of Technology and Florida International University,US) Technical Skills
Programming&Scripting:Verilog, SystemVerilog, VHDL, UVM, C/C++, python, Tcl, Perl, Makefile, shell Tools: ModelSim, VS Code, GTKWave, Klayout, Cadence, Matlab, Git, SVN, Cursor, Linux/Unix Protocals:AMBA(APB/AHB/AXI), UART, I2C, SPI
Methodology:Computer Architecture, OOP, Functional Coverage, Test Planning, LLM-driven Verification Assistance Experience
AXI4 On-Chip Interconnect Subsystem Verification 07/2024 – 06/20 DV Intern at Hebei Puhua Technology Co., Ltd.
•Developed a modular UVM verification environment for 10+ AXI4-based IPs (multi-master crossbar, width converters, protocol bridges), enabling scalable reuse and reducing integration time to <3 days per IP
•Built a Python-based RTL static analysis tool to check reset naming conventions, AXI signal completeness, and strobe/data width consistency risks, integrated as a one-command Makefile target in the CI flow
•Created constrained-random stimulus targeting complex AXI scenarios (backpressure, burst interleaving, partial writes); debugged critical protocol issues including missing B-channel responses and incorrect SLVERR signaling via waveform and transaction-level tracing
•Implemented SVA protocol checkers for AXI-Lite payload stability on valid/ready handshakes, BVALID/RVALID drop detection, and configurable liveness timeouts; connected monitors to scoreboard via analysis ports for end-to-end data integrity checking
•Developed functional coverage models with cross-coverage on normal/error paths; built automated coverage hole classification distinguish reachable vs. hard-to-hit bins from simulation logs, achieving >100% coverage across 500+ daily regression runs
•Built regression analysis and bug triage automation to parse multi-seed simulation logs, surface top failing signatures, detect flak tests, and generate Jira-ready triage reports; all tools orchestrated via Makefile for one-command execution UVM-Based Verification of Ethernet MAC 04/2026 – 08/20 RISC-V Verification Intern at Biio
•Built a modular UVM testbench for an open-source Gigabit Ethernet MAC, integrating AXI-Stream, AXI-Lite, and GMII agents with reusable drivers, monitors, and sequencers.
•Developed directed and constrained-random sequences for register configuration, packet transmission, reception, and TX/RX loopback across varying frame lengths and payload patterns.
•Implemented a CRC-32 reference model and end-to-end scoreboard to check frame data integrity and FCS correctness.
•Verified CRC error detection, short-frame handling, automatic padding, and inter-frame gap behavior through targeted test scenarios.
•Defined a verification plan and functional coverage points; integrated SVA protocol checks and regression testing to validate norma operation and corner cases.
Projects
UVM-Based Verification of 2-Way Set-Associative Cache for RISC-V
•Built a modular UVM testbench for a blocking 2-way cache RTL with val/rdy dual agents, reference model, and scoreboard; enable automated regression via Questa scripts
•Developed directed and constrained-random tests covering hit/miss/refill/evict and corner cases; resolved protocol and data mismatches via waveform-driven debug
•Implemented SVA checkers bound to DUT for req/rsp type legality, val/rdy stall stability, and bounded latency on proc and mem request/response paths
•Built automated assertion review and coverage hole analysis tooling from simulation logs, with traceability-mapped test suggestions for unreachable bins
•Achieved >100% FSM coverage across 12 states and ~16 transitions; established testplan traceability mapping features to tests, assertions, and coverage points with automated broken-link detection UVM-Based Verification of Systolic-Array GEMM Accelerator
•Built a UVM verification environment for a 16 16 systolic-array GEMM accelerator, validating end-to-end dataflow across memory load, compute pipeline, and write-back stages
•Implemented a memory BFM and golden reference model with scoreboard-based checking for accumulation correctness and write-back ordering
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