Silicon Verification Engineer (UVM/RISC-V)

VISHAL JADHAV

********@***.*** +1-602-***-**** http://www.linkedin.com/in/vishal-jadhav-b27ab71a1

OBJECTIVE

Aspiring silicon verification engineer with experience in System Verilog based-UVM testbenches, constrained-random and directed testing, and collaboration with design teams to ensure robust verification and efficient design closure. EDUCATION

Master's degree, Electrical and Electronics Engineering May 2024 Arizona State University, Tempe, Arizona GPA: 3.5/4 Relevant Coursework: VLSI Design, Digital CMOS VLSI Circuits, Hardware Design, Digital Verification and Testing, VLSI Architecture, Computer Architecture, Analog Integrated Circuits, Python for Rapid Engineering solutions Bachelor of Technology - BTech, Electrical and Electronics Engineering April 2021 B V Raju Institute of Technology, Hyderabad, India GPA: 8.9/10 SKILLS

EDA tools: ModelSim, Cadence (Virtuoso, Innovus, Spectre), Synopsys (IC Compiler II, Design Compiler, Primetime, VCS,HSPICE,Verdi), Mentor Graphics Calibre(DRC,LVS,PEX(Parasitic Extraction)), Xilinx (Vivado), QuartusPrime, Programming Languages: Python, C, C++, System Verilog(UVM, Coverages, Assertions), Verilog, shell scripting (Tcl), Perl, LINUX,Git Computer Architecture: RISC-V ISA, Processor Datapath & Control Design, Pipelined Processor Architecture, Hazard Detection & Forwarding, Cache Memory Design(Direct-Mapped, Set-Associative, Write Policies),Cache Coherency and Shared-Memory Multiprocessor Concepts

(MESI/MOESI),Virtual Memory & Address Translation (TLB, Paging), Memory Hierarchy & Cache Coherency Fundamentals, On-Chip Interconnects and Bus Protocol Concepts (AXI/AHB/APB),DMA and CPU–Memory Subsystem Interaction, Performance Optimization, Microarchitectural Tradeoffs

Protocols: APB, AHB, AXI (AMBA BUS), TileLink(TL-UL, TL-UH, TL-C), UART, SPI. PROFESSIONAL EXPERIENCE

Design Verification Engineer Western Semiconductor, Tempe, AZ Jan 2025 – Present

• Verified a Load-Store Queue (LSQ) in an out-of-order RISC-V pipeline, covering load-store ordering, store-to-load forwarding, speculative execution, and correct handling of memory hazards.

• Designed and executed directed and constrained-random UVM tests to validate corner cases including address conflicts, pipeline stalls, flushes, exceptions, and stress scenarios.

• Developed reusable UVM components, sequences, monitors, and scoreboards to validate functional correctness and protocol compliance.

• Built functional coverage models to track ordering scenarios, hazard conditions, and pipeline state transitions, using coverage results to drive verification closure.

• Verified interactions across multiple IP blocks including the LSQ, pipeline control logic, and memory interface, ensuring correct system- level behavior under stress and corner-case scenarios.

• Executed and maintained regression suites in Synopsys VCS, triaging failures and debugging waveforms in Verdi to resolve protocol violations across AMBA APB, AHB, and AXI interfaces including burst read/write operations, handshake validation, and cross-subsystem compliance checks.

IC Design Intern Central Institute of Tool Design Oct 2021 - Apr 2022

• Built foundational UVM environments (sequencer, driver, monitor, scoreboard) under senior mentorship, learning structured verification methodology through AMBA protocol (APB, AHB) and UART testbench development.

• Assisted in simulation debugging using VCS and Verdi, applying SVA assertions and coverage metrics to support verification closure under guidance.

PROJECTS

AMBA AXI3.0 Verification IP (VIP) Development SystemVerilog, UVM Fall 2025

• Developed reusable AMBA AXI3.0 Master–Slave Verification IP (VIP) with configurable Bus Functional Models (BFMs) and architected a modular UVM verification environment integrating sequencer, driver, monitor, scoreboard, and functional coverage components.

• Implemented parameterized AXI transaction class modeling all protocol channels enabling configurable stimulus generation supporting burst transfers, narrow transfers, variable burst sizes, and protocol-compliant transaction modeling.

• Verified advanced AXI protocol features including INCR/FIXED/WRAP burst types, overlapping, interleaved, and multiple outstanding transactions, validating correct out-of-order response handling using AXI ID-based tracking.

• Developed protocol-aware AXI monitor for transaction reconstruction and automated checking, performing end-to-end VIP validation by integrating Master and Slave VIP with configurable active and passive modes for protocol verification and monitoring. UVM-Based Verification for 5-Stage Pipelined RISC-V Processor Fall 2024

• Verified a 5-stage pipelined RISC-V processor using a UVM-based verification environment, validating instruction execution, pipeline hazards, and memory operations while achieving 100% functional coverage.

• Designed a comprehensive UVM testbench architecture including driver, sequencer, monitor, scoreboard, and UVM RAL model, and developed a structured test plan covering R, I, B, S, U, J instruction types, hazard detection, and corner-case scenarios.

• Automated regression, coverage collection, and debug using VCS, implementing UVM assertions and RAL-based memory verification to identify and resolve RTL issues related to control signal timing, pipeline synchronization, shift operations, and memory alignment, improving overall processor stability.

Verification and coverage of Verichip ALU Specification (Verilog, Verdi) Spring 2024

• Created a detailed test plan and corresponding test cases to verify the functionality of various register operations and FSM in Verilog based on the VeriChip specification, verifying all test cases were covered thoroughly.

• Performed a detailed code coverage analysis using Verdi and achieved 100% coverage. Evaluation of Branch Prediction Techniques and Cache Replacement Policies using Gem5 Spring 2023

• Implemented and analyzed multiple branch prediction methods in Gem5, evaluating their impact on processor performance using standard benchmarks and custom workloads, presenting results visually for clarity

• Developed and integrated the Pseudo Least Recently Used (LRUIPV) cache replacement algorithm in Gem5, utilizing the best IPV

• Conducted performance evaluations and implemented policies in C++ for accurate simulation and analysis of processor

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