RTL & Memory Verification Engineer

Saketh Ram Gandela

****************@*****.*** +1-848-***-**** http://www.linkedin.com/in/saketh-ram-gandela PROFESSIONAL SUMMARY

Design Verification Engineer with 4+ years of experience in RTL design and functional verification of digital and semiconductor systems. Hands-on experience with SystemVerilog, Verilog, UVM, Python, RTL simulation, testbench development, constrained-random verification, assertions, functional coverage, and regression testing. Experienced in DRAM, SRAM, DDR4/DDR5 concepts, Processing-in-Memory (PIM), RISC-V, memory-subsystem verification, control logic, and datapath verification. Strong background in developing verification environments, executing test scenarios, debugging RTL functionality, and analyzing design behavior using industry-standard EDA tools. Experience with 6T SRAM, CMOS circuits, transistor-level simulation, charge sharing, sense-amplifier behavior, leakage, retention, and memory timing analysis.

TECHNICAL SKILLS

• RTL & Verification: SystemVerilog, Verilog, UVM, RTL Design, Functional Verification, Testbench Development, Directed Testing, Constrained-Random Testing, SystemVerilog Assertions (SVA), Functional Coverage, Drivers, Monitors, Scoreboards, FSM Design, Datapath Design, Clock & Reset Logic, Waveform Debugging

• Memory & Digital Systems: DRAM, DDR4/DDR5, SRAM, Memory Subsystem Verification, Memory Command Sequencing, Bank Management, Address Decoding, Read/Write Operations, Timing Analysis, RISC-V

• Simulation & EDA: ModelSim, Icarus Verilog, GTKWave, Xilinx Vivado, Vivado Simulator (XSim), Vivado Hardware Manager, ILA, Quartus Prime, Cadence Virtuoso, Tanner EDA, NGSpice, HSPICE

• Programming & Automation: Python, C/C++, Tcl, Perl, MATLAB/Simulink, Regression Automation, Simulation Scripting, Log Analysis, Waveform Processing

• Analog & Semiconductor: CMOS Logic Design, Transistor-Level Simulation, Charge Sharing, Sense- Amplifier Analysis, Leakage, Retention, Transient Analysis, DRC, LVS, PEX PROFESSIONAL EXPERIENCE

DESIGN VERIFICATION ENGINEER

Analog Devices Edison, NJ, USA June 2025 – May 2026

• Worked on DRAM verification and DRAM RTL design activities using System Verilog, with focus on memory functionality and control logic.

• Developed and executed directed and constrained-random test cases covering memory commands, reset conditions, control paths, and functional scenarios.

• Performed RTL simulation, waveform analysis, and debugging to identify functional and sequencing issues in memory- related designs.

• Verified memory operations, command sequencing, address handling, and basic timing requirements against design specifications.

• Supported regression testing, analyzed failures and simulation logs, and worked with the team to resolve verification issues.

• Developed basic Python scripts to automate test execution, process simulation logs, and support verification workflows.

VERIFICATION ENGINEER

Bitsilica Hyderabad, TG, India Jun 2021 – Jul 2024

• Implemented SystemVerilog RTL modules based on functional specifications and interface requirements for semiconductor designs.

• Built module-level verification environments and reusable testbench components for checking functional behavior and interface interactions.

• Created directed and constrained-random test scenarios covering functional paths, corner cases, reset sequences, command handling, and error conditions.

• Applied SystemVerilog assertions and functional coverage to check expected behavior and identify unverified conditions.

• Automated simulation runs, test execution, and log analysis using Python to support verification and regression activities.

• Investigated RTL failures by comparing simulation behavior with expected results and tracing issues through control and datapath logic.

• Reviewed test results, coverage data, and regression status to support verification completion and project documentation.

EDUCATION

• MASTER OF SCIENCE IN COMPUTER ENGINEERING

New Jersey Institute of Technology Newark, NJ, USA

• BACHELOR OF TECHNOLOGY IN ELECTRICAL AND ELECTRONICS ENGINEERING Mahindra University Hyderabad, TG, India

PERSONAL PROJECTS

Modular DRAM Processing-in-Memory Simulation Framework

• Designed and implemented a configurable 4-bank, 64-bit SystemVerilog DRAM/PIM architecture, including command control, bank-state logic, address handling, and RowClone-style memory-copy operations.

• Developed timing-aware digital control logic with valid-ready handshaking, request stalling, row-conflict detection, error reporting, and enforcement of tRCD, tRAS, and tRP constraints.

• Built a reusable SystemVerilog/UVM self-checking verification environment with test sequences, monitors, scoreboards, and testbench components to validate normal, boundary, and illegal command scenarios.

• Verified source-to-destination RowClone operations through directed testing, regression execution, waveform debugging, and command-sequence analysis.

• Developed an NGSpice/Python analog verification flow to evaluate charge sharing, sense-amplifier restoration, leakage, retention, and RowClone functional behavior.

• Extended the framework toward a DDR-like memory architecture, creating a reusable platform for evaluating additional memory configurations and PIM operations

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