ASIC Verification Engineer Breaking RTL and Protocol Bugs

SUMMARY

Mann Marlesh Raval

ASIC Verification Engineer SoC Verification Engineer

USA +1-331-***-**** Email: *********@**************.*** LinkedIn ASIC/SoC Verification Engineer who goes after the bugs that survive normal testing: coherence-ordering corner cases, reset-recovery failures, and protocol violations. Found 20+ bugs and spec mismatches at Marvell in RISC processor subsystems and AXI interfaces. At eInfochips, cut protocol escape defects by 28% and closed functional coverage from 78% to 95% before tape-out. Builds UVM environments, SVA checkers, and Python regressions (1,000+ nightly tests). MS Electrical Engineering, RIT. PROFESSIONAL EXPERIENCE

ASIC Verification Engineer Marvell Technology USA July 2026 – Present

Developed and extended UVM/SystemVerilog components (agents, sequences, scoreboards) for the RISC processor subsystem testbench, cutting testbench-related regression failures by ~25%.

Verified the RISC processor pipeline with 40+ constrained-random instruction sequences and scoreboard checks on pipeline dependencies and hazard handling, uncovering 5 RTL bugs ahead of subsystem sign-off.

Validated cache coherence and memory consistency in single- and multi-core configurations using 25+ directed and constrained- random tests and SVA checkers on coherence-state transitions and transaction ordering, exposing 3 corner-case ordering bugs.

Verified the processor subsystem’s AMBA AXI interface through protocol compliance tests, assertions, and waveform analysis, identifying 8 functional mismatches against the spec.

Contributed to raising functional coverage on the RISC processor subsystem from 80% to 92% by adding constrained-random tests, coverage models, and 60+ SVA assertions and covergroups targeting corner cases.

Verified reset sequencing and recovery for the processor subsystem across 15+ scenarios using SVA checkers and directed tests, catching 5 reset-related bugs before integration.

Automated parts of the regression flow in Python and Shell on Synopsys VCS (Linux/HPC) for 500+ nightly tests, covering log parsing, triage, and reporting, with Git-based CI sanity checks on every commit. Debugged failures in Verdi with RTL designers. SoC Verification Engineer eInfochips India June 2021 – July 2023

Authored verification plans and UVM testbench architectures for 4 IP-level projects spanning AMBA bus and serial interface blocks, creating scalable, reusable environments across multiple semiconductor programs.

Built protocol-aware UVM monitors, drivers, and scoreboards to verify AMBA AXI, AHB, APB, SPI, UART, and I2C compliance, reducing protocol-related escape defects by 28%.

Targeted protocol corner cases with dedicated scenarios, including AXI out-of-order responses and burst types, I2C clock stretching, SPI mode variations, and UART error handling.

Verified UART and SPI across 6 baud rates and 4 clock frequency ratios, catching 3 timing and sampling mismatches at the interface boundary before integration.

Developed constrained-random tests for high-speed interface IP, raising early bug detection by 38% over the directed-test baseline.

Led pre-silicon validation using covergroups, SystemVerilog assertions, and functional coverage models across IP and SoC levels, closing functional coverage from 78% to 95% before tape-out.

Engineered regression automation frameworks using Python, Tcl, Shell scripting, Perl, and Makefiles for regression execution, log parsing, and simulation management, supporting 1,000+ tests per nightly run and reducing manual effort by nearly 45%.

Debugged RTL failures with Verdi, DVE, and QuestaSim, resolving 200+ simulation failures and improving regression stability across releases. Managed testbench code with Git and SVN across a team of 6+ engineers and tracked defects in Jira.

Contributed to ASIC-to-FPGA porting of SoC subsystem RTL in Xilinx Vivado, adapting clocking, reset, and memory models to FPGA primitives and resolving timing issues through synthesis and timing-report analysis, so firmware and driver bring-up could start early.

Correlated RTL, FPGA, and silicon behavior during bring-up and post-silicon validation, accelerating issue triage for production releases. PROJECTS

UVM Based AXI4 Verification Environment

Developed a reusable SystemVerilog UVM verification environment for an AXI4 interface using configurable agents, sequences, monitors, scoreboards, assertions, and functional coverage to validate burst transfers, responses, backpressure, and protocol corner cases.

Implemented constrained random sequences and coverage driven testing for transaction types, burst lengths, address boundaries, response conditions, and simultaneous read and write activity, achieving above 95% targeted functional coverage. Custom RISC Processor Design

Designed a 14-bit, 4-stage pipelined RISC processor in Verilog with a Von Neumann memory architecture, 4-way associative L1 cache, and memory-mapped I/O, and built a Python assembler to generate machine code and test programs for verification.

Developed a custom inter-core communication protocol for multicore memory access and validated 1-, 2-, and 4-core configurations on an FPGA, demonstrating practical understanding of multicore communication and coherency challenges. TECHNICAL SKILLS

Verification: SystemVerilog, UVM, SVA, Constrained-Random Verification, Functional & Code Coverage, Assertion-Based Verification, Coverage-Driven Verification, Verification Planning

ASIC/SoC: RTL Verification, IP & Subsystem Verification, Pre-Silicon Validation, Regression Testing, RTL Debugging, Root-Cause Analysis

Protocols: AMBA AXI4, AHB, APB, SPI, UART, I2C

Computer Architecture: RISC Pipelines, Hazard Handling, Cache Coherence, Memory Consistency, Multicore Systems

Simulation & Debug: Synopsys VCS, QuestaSim, Verdi, Waveform Analysis

Automation: Python, Shell Scripting, Tcl, Makefile, Regression Automation, Log Parsing, Failure Triage

Verification Analysis: Coverage Closure, Code Coverage, Root-Cause Analysis

Environment: Linux, HPC, Git, SVN, CI, Jira

FPGA & Bring-Up: FPGA Prototyping (Xilinx Vivado), ASIC-to-FPGA Porting, Synthesis and Timing Analysis, RTL/FPGA/Silicon Correlation

Hardware: RTL Design, FSM, Logic Synthesis, Memory Verification, FPGA Prototyping (Xilinx Vivado) EDUCATION

Master of Science in Electrical Engineering

Rochester Institute of Technology, Rochester, New York, USA Jan 2024 – Dec 2025 Bachelor's in Electronics and Communication Engineering Nirma University, Ahmedabad, Gujarat, India July 2019 – May 2023 PUBLICATIONS

Assembler for 8086 Microprocessor using Python July 12, 2022 OFDM Technique for Efficient Image Transmission over Fading Channels for Different Modulation Schemes June 29, 2022

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