GPU Design Verification Engineer

BHAVYA REDDY GANDHETI

California, CA,***** 971-***-**** ******************@*****.***

OBJECTIVE

GPU Design Verification Engineer with experience in System Verilog, UVM, SVA, formal verification, RTL debugging, and functional coverage. Skilled in GPU IP verification, digital design concepts, debugging RTL designs, and achieving coverage closure.

WORK EXPERIENCE

GPU Design Verification Engineer: Intel Corporation Jan’2025 – Present

• Performed formal verification of sampler rtl using FPV and RTL2RTL equivalence checking, developing TCL flows, SVA assertions and environment assumptions to validate functional correctness.

• Developed and executed clock gating formal verification for sampler units by building TCL flows, adding assumptions and debugged formal failures to ensure correct clock gating behavior.

• Analyzed simulation waveforms and traced signals across sampler stages to quickly identify and resolve RTL design issues.

• Developed functional coverage for sampler IP, debugged and analyzed unhit bins, and implemented coverage improvements to enhance overall coverage closure. Design Verification Engineer: Intel Corporation Feb’21 – Nov’22 Packet Processing Building Blocks

• Conducted thorough verification of Switch-IP, adhering to verification test plan and design specifications.

• Developed directed testcases, comprehensive testcases to improve functional and code coverage.

• Developed UVM verification environment components including Driver, Monitor and Scoreboard.

• Identified gaps in the coverage goals and implemented tests to improve the coverage towards the project goals.

• Collaborated with the design team along with the architecture teams to understand the new features and developed tests to verify the new features.

• Diagnosed failures in the testbench environment and root-caused the issues. PROJECTS

Design and Verification of an I2C based Memory Subsystem

• Implemented an I2C based memory subsystem in System Verilog.

• Designed I2C master and slave modules using Moore FSMs.

• Implemented an 8-bit Universal Shift Register as the functional unit to drive inputs to Memory subsystem.

• Verified the system using SV environment, used System Verilog Assertions and Coverage. Design and Verification of Asynchronous FIFO

• Developed a detailed verification test plan for an asynchronous FIFO, including design specification, methodologies, and strategies to ensure functionality and performance.

• Tested FIFO Exhaustively using System Verilog and UVM with write clock and read clock as 240MHZ and 400MHZ respectively.

• Validated the test scenarios and functionality from the simulation waveform using Questa sim.

• Improved Verification coverage from 70% to 85% by implementing additional testcase scenarios and merging coverage metrics for complete validation.

EDUCATION

Portland State University, Oregon, USA Jan’23 – Dec’24 M.S.Electrical and Computer Engineering GPA:3.74/4.0 Course work: Introduction to System Verilog, Fundamentals of Pre-Silicon Validation (UVM), Assertion Based Verification. TECHNICALSKILLS

Hardware Languages: Verilog, System Verilog

Assertion Languages: SVA

Methodology: UVM

Scripting: Python

Tools: Synopsys VCS, Questa sim, Model Sim, Jasper Gold Verdi Concepts: Advanced Digital Design using Verilog, Environment based verification, Functional Coverage, Object oriented programming, Constraint Randomization, System Verilog Assertions (SVA), AMBA (APB, AXI).

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