UVM Design & Verification Engineer

Jaishyam Reddy Reddivari Design & Verification Engineer Boston, MA (open to relocation)

+1-331-***-**** *****************@*****.*** linkedin.com/in/jaishyam-reddy-reddivari/ github.com/JaishyamReddivari PROFESSIONAL SUMMARY

MS Computer Engineering graduate with five UVM environments spanning a systolic-array ML accelerator, AXI4, RISC-V, CDC FIFO, and UART/RAL. Built constrained-random testbenches, reference-model scoreboards, and Python regression infrastructure, with waveform root-cause debugging across RTL, TB, and RAL layers. EDUCATION

Syracuse University, Syracuse, NY Jan 2024 – Dec 2025 Master of Science in Computer Engineering GPA: 3.6/4 Relevant Coursework: Computer Architecture, Embedded Systems Design, SoC Design, VLSI CAD, Digital Electronic Circuits, Analog Electronic Circuits, Advanced Data Structures and Algorithms Osmania University, Hyderabad, India Aug 2019 – Jun 2023 Bachelor of Engineering, Electrical and Electronics Engineering GPA: 3.4/4 TECHNICAL SKILLS

• Programming Languages: SystemVerilog, Verilog, C++, Python, Shell/Bash

• Protocols: AMBA (AXI4Full/Lite/Stream, AHB, APB), UART, SPI, I2C

• Tools: Questa/ModelSim, VCS, Riviera-PRO, Verilator, Vivado, Linux, Git, Makefiles, KiCAD, Surfer

• Methodologies: Constrained-Random, Functional & Code Coverage, UVM, RAL, SVA, CDC, STA, UPF Power Aware Design & Verification (IEEE 1801)

PROJECTS

8x8 INT8 Systolic-Array Accelerator - Design & UVM Verification (Verilator, VCS, UVM, Python, C++)

• Built a UVM environment for an 8x8 INT8 weight-stationary systolic-array ML accelerator (AXI4-Stream + AXI4- Lite), closing 100% functional and 97.1% line coverage on Verilator, with a VCS portability check

• Drove constrained-random stimulus into a self-checking scoreboard cross-validated by three reference models

(NumPy, cycle-accurate, C++); caught a dataflow spec bug before writing RTL

• Built a hand-rolled functional-coverage model and a Python regression runner; a vacuous-pass guard — failing any test with zero scoreboard comparisons — caught a phase-objection bug, then ran a clean 500-seed regression

• Authored SVA assertions and cover properties on the 7-state controller FSM, including a producer/consumer guarantee that COMPUTE never starts on a partial input tile AXI4 Slave UVM Black-Box Verification (Riviera-PRO, VCS)

• Built a UVM black-box environment to verify a reference AXI4 slave-RAM RTL (ARM spec), exercising 56 protocol features across 22 directed + constrained-random tests

• Architected a byte-addressable associative-array reference scoreboard (burst, partial-write, boundary, multi-ID) and 14 SVA assertions for handshake, response, and reset-recovery correctness

• Closed 97.5% functional coverage (5 covergroups) across 5 parameterized DUT configurations; ran on Riviera- PRO with a VCS portability check

RISC-V 5-Stage Pipelined Processor - Design & Verification (Riviera-PRO, Python)

• Designed and verified a self-built 5-stage RV32I core with a UVM environment (dual agents, ISA reference scoreboard, pipeline-internal exec monitor), passing all 31 instructions with zero mismatches

• Detected a register-file write-read bypass bug causing stale reads via scoreboard + waveform analysis; authored 28 SVA assertions for forwarding, load-use stalls, flush timing, and PC integrity

• Improved functional coverage 52% 96% across 19 covergroups with 10 targeted hazard and control-flow sequences, backed by a Python multi-seed regression framework UART 16550 Controller - RTL Design & Verification (SystemVerilog, UVM, RAL)

• Engineered a PC16550D-compatible UART 16550 controller in SystemVerilog — TX/RX state machines, programmable baud generator, FIFO buffering

• Built a UVM environment with a dual-address-map RAL for DLAB register aliasing (adapter/predictor), verifying 500 constrained-random frames with zero mismatches

• Root-caused and resolved 17 RTL design defects (FIFO pointer errors, baud-generator races) plus testbench/RAL integration issues via scoreboard and waveform debugging Asynchronous CDC FIFO Design & Verification (Vivado, Verilog, SystemVerilog)

• Designed a 16-deep async CDC FIFO with Gray-coded pointers, dual-clock domains, and 2-FF synchronizers for metastability protection and full/empty/overrun/underrun flags; synthesized in Vivado

• Built a UVM verification environment with dual-clock-domain forked monitors, FIFO-queue reference scoreboard, and constrained-random stimulus verifying data integrity across asymmetric clock ratios; achieved 0 mismatches EXPERIENCE

Hardware Design Engineer, Q’s Ministry/BHITS, Remote (KiCAD) Feb 2026 – Present

• Leading hardware design for a dual-channel embedded DC motor-controller board (KiCAD) — schematic capture, power-protection and current-sensing subsystems; coordinating one junior engineer

• Ran design review catching component- and pin-level errors pre-layout, applying verification rigor to hardware

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