Pre-Silicon Verification Engineer (UVM/SystemVerilog)

Tharun R. Mopuru

513-***-**** *****************@*****.*** linkedin.com/in/tharunrm github.com/Tharunreddym TECHNICAL SKILLS

SystemVerilog, Verilog, SystemVerilog OOP, UVM, C++, C, Python, Embedded C, Linux, Git Pre-Silicon Ver- ification, RTL Verification, SoC Verification, Verification Planning, UVM Testbench Development, Constrained- Random Verification, Coverage-Driven Verification, Functional Coverage, SVA, Assertions, Scoreboards, Reference Models, Protocol Verification, Regression Automation Computer Architecture, Processor Verification, RISC-V, CPU Pipelines, Memory Systems, SRAM, AXI4, DDR4/DDR5, PCIe, Ethernet MAC DPI-C, Formal Veri- fication, Gate-Level Simulation, Waveform Debug, Timing Debug, Regression Analysis QuestaSim, Synopsys VCS/Verdi, pytest

EXPERIENCE

Embedded Verification Engineer India

Bosch Jun 2023 – Jul 2024

• Developed and executed 100+ validation tests for embedded firmware and UART, SPI, I2C, and CAN interfaces across functional, boundary, regression, and fault scenarios.

• Automated regression execution, log analysis, and failure triage with Python and pytest, reducing manual val- idation effort by 40%; debugged hardware-software failures using waveforms, logic analyzers, and oscilloscopes. Design Verification Intern India

Maven Silicon May 2022 – Jan 2023

• Developed 5+ reusable SystemVerilog/UVM components using SystemVerilog OOP for AMBA RTL verification, including sequences, drivers, monitors, scoreboards, and functional coverage.

• Built and debugged UVM testbenches and executed 15+ directed and constrained-random tests using SVA, assertions, scoreboards, waveform analysis, and regression triage for SoC RTL blocks.

• Performed gate-level simulation and formal property verification, analyzing timing failures and improving ver- ification coverage across RTL and gate-level regressions. PROJECTS

RISC-V CPU RTL Design & Verification GitHub

SystemVerilog · UVM · RISC-V RV32I · C++ · DPI-C · QuestaSim

• Owned verification of a 5-stage RV32I CPU using UVM, constrained-random stimulus, SVA, scoreboards, and functional coverage for hazards, forwarding, and corner cases.

• Root-caused and fixed a RAW forwarding defect through waveform analysis, validating 20 seeds and 800 instructions with zero UVM errors and zero scoreboard mismatches. High-Speed SoC I/O & Memory Subsystem Verification GitHub SystemVerilog · UVM · DDR4/DDR5 · Ethernet MAC · PCIe · AXI4 · SVA · Python

• Developed a reusable UVM environment for DDR4/DDR5-style memory, 10GbE MAC, and PCIe endpoint verification with protocol monitors, scoreboards, and reference models.

• Executed 30+ tests across 20+ seeds and 25K+ transactions using constrained-random stimulus, SVA, func- tional coverage, and Python regression automation for DDR, Ethernet, and PCIe corner cases. AXI4 Memory Controller UVM Verification GitHub

SystemVerilog · UVM · AXI4 · SVA · Python · QuestaSim

• Developed and verified an AXI4 memory-controller environment covering transfers, bursts, handshakes, order- ing, and data consistency using constrained-random stimulus, SVA, monitors, and scoreboards.

• Resolved a burst-read scoreboard mismatch through waveform debug and root-cause analysis, validating 780 AXI4 beats with zero final mismatches.

SRAM Subsystem Verification GitHub

SystemVerilog · UVM · SVA · Python · QuestaSim

• Developed a coverage-driven UVM environment for SRAM verification, covering boundary, back-to-back, ran- domized, and read-after-write scenarios using SVA, functional coverage, and a shadow-memory model.

• Executed 22 QuestaSim simulations across directed and 20-seed random regressions, validating 30K+ transac- tions with zero mismatches and 84.3% peak functional coverage. EDUCATION

University of Cincinnati, Cincinnati, OH Aug 2024 – Jul 2026 Master of Engineering in Computer Engineering

Relevant Coursework: Embedded Systems, Microprocessors, Computer Architecture, VLSI, Circuit Design

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