GPU SoC Verification Engineer (UVM/CHI)

SRI DURGA RAJU

Houston, TX 515-***-**** LinkedIn github **************@*****.***

SKILLS & CERTIFICATIONS

Verification: UVM, constrained-random test generation, directed testing, white-box/black-box testing, SVA/ABV, RAL, functional & code coverage closure, formal property verification, C/C++ DPI transactors, C/C++ reference models, synthesizable BFMs, monitors & checkers, data structures, object-oriented programming, verification metrics & test planning, pre-silicon & post-silicon validation, regression debug, root cause analysis

CPU-GPU Arch & Coherency: ARM CHI (RN/HN/SN), MESI cache coherence, CPU-GPU coherency, memory ordering & consistency, OoO execution, speculative execution, branch prediction, cache hierarchy, address translation, IPC/CPI Protocols: AXI3/4, AHB, APB, ARM CHI, SPI, I2C, I3C, UART, DDR Emulation / Prototyping: FPGA-based emulation bring-up (PYNQ-Z2 ARM Cortex-A9), Xilinx Vivado RTL-to-FPGA Languages & Tools: C, C++, SystemVerilog, Verilog, VHDL, Python, Perl, RISC-V Assembly; Questa, ModelSim, Synopsys DC, Xilinx Vivado, VCS, Git, Linux; GitHub Copilot, LLM-assisted debug & scripting WORK EXPERIENCE

KGS Technology Group, Inc Jul 2025 - Present

Design Verification Engineer

• Test plan & infrastructure: Defining strategy and authoring unit-level and chip-level test plans for GPU rasterization engine verification; building portable UVM infrastructure with C/C++ DPI transactors, synthesizable BFMs, monitors, checkers, scoreboards, and coverage collectors, driving functional and assertion coverage closure across GPU pipeline stages.

• GPU SoC DV: Verifying GPU rasterization and imaging pipeline in a graphics SoC using UVM; validating cache coherency, memory ordering, and latency corner cases across pipeline stages in collaboration with RTL designers; writing monitors and checkers to aid debug in HW test issues and FW/SW bring-up.

• Random test generation & CHI DV: Developing constrained-random test generators and directed test sequences for ARM CHI-based coherent interconnect verifying CPU–GPU coherency; root-causing RTL failures through waveform debug in Git-tracked regression environment.

University of Houston - Department of Electrical and Computer Engineering Houston, TX Research Assistant Sep 2024 - Jul 2025

• Designed and verified SPI-based memory controller on PYNQ-Z2 FPGA (ARM Cortex-A9 SoC) in Xilinx Vivado; executed full RTL-to- FPGA flow mirroring emulation bring-up on a Linux-based embedded environment; supported post-silicon validation and system-level failure debug using oscilloscopes, logic analyzers, and protocol analyzers.

• Developed reusable Python and Perl automation tooling to characterize ReRAM read/write latency, endurance, and power across test configurations; analyzed waveforms via protocol analyzers to accelerate silicon debug and coverage reporting, enabling repeatable use across future characterization runs.

SION Semiconductors India

SoC Verification Engineer Mar 2021 - Sep 2021

• Authored test plans for AXI, SPI, and I2C protocol IP interconnects verification; developed UVM testbenches with 10+ constrained-random test generators, C/C++ DPI transactors, and SVA assertions in QuestaSim; improved functional coverage closure by 20% across CPU subsystem components.

• Synthesized FIFO and ALU RTL using Synopsys DC; achieved 15% leakage power reduction through low-power PPA analysis; executed GLS post-synthesis verification flow.

Maven Silicon India

Digital Design Intern Dec 2020 - Jan 2021

• Developed and executed 15+ functional test cases for AHB-to-APB Bridge IP covering single/burst read/write transfers, achieving 100% functional coverage, integrated IP into SoC architecture using ModelSim. PROJECT EXPERIENCE

CHI Coherent Interconnect Verification – CPU-GPU Coherency DV Mar 2026 – Present

• Implementing three-node ARM CHI system (RN/HN/SN) verifying CPU-GPU coherency in Xilinx Vivado; modeling MESI coherence states with synthesizable BFMs, monitors, and SVA checkers targeting snoop filter interactions, directory updates, and memory ordering corner cases. Tracking functional and assertion coverage toward 100% closure; root-causing coherency violations through waveform debug and regression analysis.

RISC-V 5-Stage Pipeline Processor – Microarchitecture Design & Verification Feb 2026 – Present

• Architecting 5-stage RISC-V pipeline (IF/ID/EX/MEM/WB) with ALU, branch unit, forwarding network, and hazard detection; validated 60+ ISA compliance tests in ModelSim with SVA formal property checkers on hazard logic.

• Instrumenting pipeline performance counters for IPC/CPI analysis. Memory Controller & MESI DV – UVM RAL + Block-Level Verification Jan 2025 – May 2025

• Built UVM testbench with RAL model, predictors, monitors, and scoreboard for SystemVerilog memory controller; drove functional coverage to 90% through constrained-random test generators and directed scenarios. Verified dual-core MESI protocol with 100% assertion coverage in QuestaSim; developed C++ two-level cache simulator achieving 65% L1 miss rate reduction and 33% lower AMAT. CPU Performance Analysis – OoO Architecture & Cache Exploration Jan 2024 – May 2024

• Analyzed OoO processor performance using SimpleScalar across 10 SPEC2000 benchmarks; evaluated L1/L2 cache, associativity, block size, and TLB configurations on IPC and cache miss rates; identified optimal configurations yielding 30% IPC improvement and 25% reduction in cache misses, directly characterizing high-performance CPU power/performance trade-offs. EDUCATION

University of Houston, TX - Master of Science, Computer and Systems Engineering May 2024 Related courses: Hardware Verification, Advanced Computer Architecture, Digital Logic Design, VLSI design CGPA: 3.67 / 4.00 Amrita Vishwa Vidyapeetham, India - Bachelor of Technology, Electronics and Communication Engineering

Contact this candidate