PCIe Gen5 & I2C Protocol Verification Engineer

NAVEEN KUMAR REDDY THUMMALA

Design Verification Engineer PCIe & I2C Protocol Verification

******************@*****.*** +1-503-***-**** LinkedIn San Jose, CA PROFESSIONAL SUMMARY

Design Verification Engineer with 3+ years of ASIC/IP verification experience specializing in PCIe Gen5 Data Link Layer and I2C protocol verification using System Verilog, UVM, and SVA. Proven track record of driving functional coverage closure from the 75-80% range to 90-95% through constrained-random and directed test development, self-checking scoreboards, and targeted error-injection scenarios. Skilled in root-causing complex RTL failures using Synopsys VCS/Verdi waveform debugging and AI-assisted debug flows, cutting average issue-triage time by roughly 25%. Experienced partnering directly with RTL design teams through daily triage and milestone reviews to close out verification sign-off on schedule.

TECHNICAL SKILLS

• Verification Languages: System Verilog, Verilog, C, C++

• Verification Methodologies: UVM, OVM, Constrained-Random Verification (CRV), Coverage-Driven Verification (CDV), Assertion-Based Verification (SVA), Formal Verification

• EDA & Simulation Tools: Synopsys VCS, Synopsys Verdi (incl. AI-assisted root-cause debug), Cadence Xcelium, Siemens/Mentor Questa, Veloce Strato (Emulation), Synopsys VC Formal, Cadence Jasper Gold

• Protocols & Interfaces: PCIe (Gen4/Gen5), AMBA (AHB, APB, AXI), I2C, UART, SPI, Ethernet

• Scripting & Automation: Python, Perl, TCL, Shell, Make files, Jenkins (regression CI/CD)

• AI-Assisted Verification: Verdi AI-based waveform root-cause analysis, Python-driven regression triage and log-parsing automation, LLM-assisted test-plan and coverage-gap review

• Debug, PM & Version Control: Waveform Debugging, Functional/Code Coverage Analysis, JIRA, Confluence, Git, perforce (P4)

PROFESSIONAL EXPERIENCE

Etched Design Verification Engineer San Jose, CA June 2025 – Present Project: PCIe Gen5 Data Link Layer IP Verification

• Developed and executed 50+ directed and constrained-random UVM test cases to verify PCIe Gen5 TLP/DLLP transfer, ACK/NAK handshaking, sequence-number management, LCRC generation/checking, and replay mechanisms, driving Data Link Layer functional coverage to 95%.

• Enhanced the UVM testbench architecture by reworking sequences, virtual sequencers, stimulus generators, scoreboard checkers, and error-injection scenarios, improving component reusability across DLL sub-modules by approximately 30%.

• Built self-checking test suites targeting LCRC error injection, NAK response handling, replay-buffer operation, replay-timer expiry, and TLP retransmission, cutting manual result-verification effort by roughly 40%.

• Debugged regression failures using UVM logs, System Verilog Assertions (SVA), and Synopsys Verdi waveform and AI-assisted root-cause analysis, reducing average issue-triage time by approximately 25%.

• Analyzed functional and code coverage reports in VCS/Verdi, identified coverage holes in DLL retry and flow- control logic, and added 20+ targeted tests, raising overall coverage closure from 80% to 95%.

• Planned and executed nightly and full-suite regressions of 500+ tests spanning normal, back-to-back, error- injection, and recovery scenarios, and verified RTL bug fixes through regression reruns.

• Partnered with RTL design engineers in daily triage sessions to reproduce protocol failures, isolate root causes, and confirm testbench or RTL fixes ahead of milestone sign-off.

• Authored and maintained verification plans, test-case specifications, and coverage-closure reports in JIRA/Confluence to support milestone reviews and design sign-off readiness. Environment: System Verilog, UVM, SVA, Synopsys VCS, Synopsys Verdi, PCIe Gen5, Python, Perl, Git, JIRA, Confluence, Linux

Sevya Multimedia Design Verification Engineer India Jul 2022 – Nov 2023 Project: I2C Controller and Target IP Verification

• Performed IP-level verification of an I2C Controller and Target design using System Verilog and UVM, building a modular, protocol-compliant testbench aligned to internal verification standards.

• Developed 40+ directed and self-checking UVM test cases covering read/write transactions, START/STOP conditions, ACK/NACK handling, and repeated-START scenarios, reaching over 90% functional coverage.

• Verified 7-bit addressing and data-transfer accuracy across Standard-mode (100 KHz), Fast-mode (400 KHz), and Fast-mode Plus (1 MHz) SCL frequencies, confirming protocol-compliant timing at every speed grade.

• Created and validated test scenarios for clock stretching, multi-master arbitration, bus-busy detection, and arbitration-loss recovery to confirm robust behavior under multi-master bus conditions.

• Designed error-injection and recovery tests for NACK responses, invalid address access, and incomplete transfers, improving RTL error-handling robustness and reducing escaped defects by approximately 35%.

• Executed simulation regressions in Synopsys VCS, debugged failures through logs and Verdi waveform analysis, and verified RTL fixes across successive regression cycles.

• Analyzed functional and code coverage metrics, closed identified gaps with targeted test cases, and improved overall IP coverage from roughly 75% to 92%.

• Maintained verification IP, testbenches, and automation scripts in Perforce (P4), supporting version control, peer code reviews, and collaborative development with cross-functional teams. Environment: System Verilog, UVM, Synopsys VCS, Synopsys Verdi, I2C Protocol, Python, Perforce (P4), JIRA, Linux EDUCATION

• Master of Science in Electrical and Computer Engineering — Portland State University, Portland, OR

• Bachelor of Engineering in Electronics and Communication Engineering — Visvesvaraya Technological University, India

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